forked from mfulz_github/qmk_firmware
Remove missed timer 0 init code in the ISP protocol handler in the AVRISP project. Switch the XPROG protocol target communications handler over to using Timer 1 COMA/COMB ISRs for the two physical layers, rather than COMA/ICR1. Speed up bit-banged USART mode slightly.
This commit is contained in:
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8cd7e118e9
commit
022035839e
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@ -122,9 +122,6 @@ uint8_t ISPTarget_WaitForProgComplete(const uint8_t ProgrammingMode, const uint1
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break;
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case PROG_MODE_WORD_VALUE_MASK:
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case PROG_MODE_PAGED_VALUE_MASK:
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TCNT0 = 0;
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TIFR0 = (1 << OCF1A);
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do
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{
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SPI_SendByte(ReadMemCommand);
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@ -57,13 +57,13 @@
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/* Macros: */
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/** Programmer ID string, returned to the host during the CMD_SIGN_ON command processing */
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#define PROGRAMMER_ID "AVRISP_MK2"
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#define PROGRAMMER_ID "AVRISP_MK2"
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/** Timeout period for each issued command from the host before it is aborted */
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#define COMMAND_TIMEOUT_MS 200
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#define COMMAND_TIMEOUT_MS 200
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/** Command timeout counter register, GPIOR for speed */
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#define TimeoutMSRemaining GPIOR1
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#define TimeoutMSRemaining GPIOR0
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/* External Variables: */
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extern uint32_t CurrentAddress;
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@ -49,52 +49,6 @@ volatile uint16_t SoftUSART_Data;
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#define SoftUSART_BitCount GPIOR2
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/** ISR to manage the TPI software USART when bit-banged TPI USART mode is selected. */
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ISR(TIMER1_CAPT_vect, ISR_BLOCK)
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{
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/* Toggle CLOCK pin in a single cycle (see AVR datasheet) */
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BITBANG_TPICLOCK_PIN |= BITBANG_TPICLOCK_MASK;
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/* If not sending or receiving, just exit */
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if (!(SoftUSART_BitCount))
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return;
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/* Check to see if we are at a rising or falling edge of the clock */
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if (BITBANG_TPICLOCK_PORT & BITBANG_TPICLOCK_MASK)
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{
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/* If at rising clock edge and we are in send mode, abort */
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if (IsSending)
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return;
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/* Wait for the start bit when receiving */
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if ((SoftUSART_BitCount == BITS_IN_USART_FRAME) && (BITBANG_TPIDATA_PIN & BITBANG_TPIDATA_MASK))
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return;
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/* Shift in the bit one less than the frame size in position, so that the start bit will eventually
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* be discarded leaving the data to be byte-aligned for quick access */
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if (BITBANG_TPIDATA_PIN & BITBANG_TPIDATA_MASK)
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SoftUSART_Data |= (1 << (BITS_IN_USART_FRAME - 1));
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SoftUSART_Data >>= 1;
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SoftUSART_BitCount--;
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}
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else
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{
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/* If at falling clock edge and we are in receive mode, abort */
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if (!IsSending)
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return;
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/* Set the data line to the next bit value */
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if (SoftUSART_Data & 0x01)
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BITBANG_TPIDATA_PORT |= BITBANG_TPIDATA_MASK;
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else
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BITBANG_TPIDATA_PORT &= ~BITBANG_TPIDATA_MASK;
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SoftUSART_Data >>= 1;
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SoftUSART_BitCount--;
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}
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}
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/** ISR to manage the PDI software USART when bit-banged PDI USART mode is selected. */
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ISR(TIMER1_COMPA_vect, ISR_BLOCK)
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{
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@ -119,7 +73,7 @@ ISR(TIMER1_COMPA_vect, ISR_BLOCK)
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/* Shift in the bit one less than the frame size in position, so that the start bit will eventually
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* be discarded leaving the data to be byte-aligned for quick access */
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if (BITBANG_PDIDATA_PIN & BITBANG_PDIDATA_MASK)
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SoftUSART_Data |= (1 << (BITS_IN_USART_FRAME - 1));
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((uint8_t*)&SoftUSART_Data)[1] |= (1 << (BITS_IN_USART_FRAME - 9));
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SoftUSART_Data >>= 1;
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SoftUSART_BitCount--;
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@ -131,7 +85,7 @@ ISR(TIMER1_COMPA_vect, ISR_BLOCK)
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return;
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/* Set the data line to the next bit value */
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if (SoftUSART_Data & 0x01)
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if (((uint8_t*)&SoftUSART_Data)[0] & 0x01)
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BITBANG_PDIDATA_PORT |= BITBANG_PDIDATA_MASK;
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else
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BITBANG_PDIDATA_PORT &= ~BITBANG_PDIDATA_MASK;
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@ -140,49 +94,53 @@ ISR(TIMER1_COMPA_vect, ISR_BLOCK)
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SoftUSART_BitCount--;
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}
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}
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#endif
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/** Enables the target's TPI interface, holding the target in reset until TPI mode is exited. */
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void XPROGTarget_EnableTargetTPI(void)
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/** ISR to manage the TPI software USART when bit-banged TPI USART mode is selected. */
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ISR(TIMER1_COMPB_vect, ISR_BLOCK)
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{
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/* Set /RESET line low for at least 90ns to enable TPI functionality */
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RESET_LINE_DDR |= RESET_LINE_MASK;
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RESET_LINE_PORT &= ~RESET_LINE_MASK;
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asm volatile ("NOP"::);
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asm volatile ("NOP"::);
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/* Toggle CLOCK pin in a single cycle (see AVR datasheet) */
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BITBANG_TPICLOCK_PIN |= BITBANG_TPICLOCK_MASK;
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#if defined(XPROG_VIA_HARDWARE_USART)
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/* Set Tx and XCK as outputs, Rx as input */
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DDRD |= (1 << 5) | (1 << 3);
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DDRD &= ~(1 << 2);
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/* Set up the synchronous USART for XMEGA communications -
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8 data bits, even parity, 2 stop bits */
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UBRR1 = (F_CPU / 1000000UL);
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UCSR1B = (1 << TXEN1);
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UCSR1C = (1 << UMSEL10) | (1 << UPM11) | (1 << USBS1) | (1 << UCSZ11) | (1 << UCSZ10) | (1 << UCPOL1);
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/* If not sending or receiving, just exit */
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if (!(SoftUSART_BitCount))
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return;
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/* Send two BREAKs of 12 bits each to enable TPI interface (need at least 16 idle bits) */
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XPROGTarget_SendBreak();
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XPROGTarget_SendBreak();
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#else
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/* Set DATA and CLOCK lines to outputs */
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BITBANG_TPIDATA_DDR |= BITBANG_TPIDATA_MASK;
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BITBANG_TPICLOCK_DDR |= BITBANG_TPICLOCK_MASK;
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/* Check to see if we are at a rising or falling edge of the clock */
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if (BITBANG_TPICLOCK_PORT & BITBANG_TPICLOCK_MASK)
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{
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/* If at rising clock edge and we are in send mode, abort */
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if (IsSending)
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return;
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/* Wait for the start bit when receiving */
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if ((SoftUSART_BitCount == BITS_IN_USART_FRAME) && (BITBANG_TPIDATA_PIN & BITBANG_TPIDATA_MASK))
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return;
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/* Set DATA line high for idle state */
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BITBANG_TPIDATA_PORT |= BITBANG_TPIDATA_MASK;
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/* Shift in the bit one less than the frame size in position, so that the start bit will eventually
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* be discarded leaving the data to be byte-aligned for quick access */
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if (BITBANG_TPIDATA_PIN & BITBANG_TPIDATA_MASK)
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((uint8_t*)&SoftUSART_Data)[1] |= (1 << (BITS_IN_USART_FRAME - 9));
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/* Fire timer capture ISR every 100 cycles to manage the software USART */
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OCR1A = 100;
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TCCR1B = (1 << WGM13) | (1 << WGM12) | (1 << CS10);
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TIMSK1 = (1 << ICIE1);
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/* Send two BREAKs of 12 bits each to enable TPI interface (need at least 16 idle bits) */
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XPROGTarget_SendBreak();
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XPROGTarget_SendBreak();
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#endif
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SoftUSART_Data >>= 1;
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SoftUSART_BitCount--;
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}
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else
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{
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/* If at falling clock edge and we are in receive mode, abort */
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if (!IsSending)
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return;
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/* Set the data line to the next bit value */
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if (((uint8_t*)&SoftUSART_Data)[0] & 0x01)
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BITBANG_TPIDATA_PORT |= BITBANG_TPIDATA_MASK;
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else
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BITBANG_TPIDATA_PORT &= ~BITBANG_TPIDATA_MASK;
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SoftUSART_Data >>= 1;
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SoftUSART_BitCount--;
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}
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}
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#endif
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/** Enables the target's PDI interface, holding the target in reset until PDI mode is exited. */
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void XPROGTarget_EnableTargetPDI(void)
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@ -216,8 +174,8 @@ void XPROGTarget_EnableTargetPDI(void)
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asm volatile ("NOP"::);
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asm volatile ("NOP"::);
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/* Fire timer compare ISR every 100 cycles to manage the software USART */
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OCR1A = 100;
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/* Fire timer compare channel A ISR every 90 cycles to manage the software USART */
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OCR1A = 90;
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TCCR1B = (1 << WGM12) | (1 << CS10);
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TIMSK1 = (1 << OCIE1A);
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@ -227,6 +185,71 @@ void XPROGTarget_EnableTargetPDI(void)
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#endif
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}
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/** Enables the target's TPI interface, holding the target in reset until TPI mode is exited. */
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void XPROGTarget_EnableTargetTPI(void)
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{
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/* Set /RESET line low for at least 90ns to enable TPI functionality */
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RESET_LINE_DDR |= RESET_LINE_MASK;
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RESET_LINE_PORT &= ~RESET_LINE_MASK;
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asm volatile ("NOP"::);
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asm volatile ("NOP"::);
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#if defined(XPROG_VIA_HARDWARE_USART)
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/* Set Tx and XCK as outputs, Rx as input */
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DDRD |= (1 << 5) | (1 << 3);
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DDRD &= ~(1 << 2);
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/* Set up the synchronous USART for XMEGA communications -
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8 data bits, even parity, 2 stop bits */
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UBRR1 = (F_CPU / 1000000UL);
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UCSR1B = (1 << TXEN1);
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UCSR1C = (1 << UMSEL10) | (1 << UPM11) | (1 << USBS1) | (1 << UCSZ11) | (1 << UCSZ10) | (1 << UCPOL1);
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/* Send two BREAKs of 12 bits each to enable TPI interface (need at least 16 idle bits) */
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XPROGTarget_SendBreak();
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XPROGTarget_SendBreak();
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#else
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/* Set DATA and CLOCK lines to outputs */
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BITBANG_TPIDATA_DDR |= BITBANG_TPIDATA_MASK;
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BITBANG_TPICLOCK_DDR |= BITBANG_TPICLOCK_MASK;
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/* Set DATA line high for idle state */
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BITBANG_TPIDATA_PORT |= BITBANG_TPIDATA_MASK;
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/* Fire timer capture channel B ISR every 90 cycles to manage the software USART */
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OCR1B = 9;
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TCCR1B = (1 << WGM12) | (1 << CS10);
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TIMSK1 = (1 << OCIE1B);
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/* Send two BREAKs of 12 bits each to enable TPI interface (need at least 16 idle bits) */
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XPROGTarget_SendBreak();
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XPROGTarget_SendBreak();
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#endif
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}
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/** Disables the target's PDI interface, exits programming mode and starts the target's application. */
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void XPROGTarget_DisableTargetPDI(void)
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{
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#if defined(XPROG_VIA_HARDWARE_USART)
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/* Turn off receiver and transmitter of the USART, clear settings */
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UCSR1A |= (1 << TXC1) | (1 << RXC1);
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UCSR1B = 0;
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UCSR1C = 0;
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/* Set all USART lines as input, tristate */
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DDRD &= ~((1 << 5) | (1 << 3));
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PORTD &= ~((1 << 5) | (1 << 3) | (1 << 2));
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#else
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/* Set DATA and CLOCK lines to inputs */
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BITBANG_PDIDATA_DDR &= ~BITBANG_PDIDATA_MASK;
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BITBANG_PDICLOCK_DDR &= ~BITBANG_PDICLOCK_MASK;
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/* Tristate DATA and CLOCK lines */
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BITBANG_PDIDATA_PORT &= ~BITBANG_PDIDATA_MASK;
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BITBANG_PDICLOCK_PORT &= ~BITBANG_PDICLOCK_MASK;
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#endif
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}
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/** Disables the target's TPI interface, exits programming mode and starts the target's application. */
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void XPROGTarget_DisableTargetTPI(void)
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{
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RESET_LINE_PORT &= ~RESET_LINE_MASK;
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}
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/** Disables the target's PDI interface, exits programming mode and starts the target's application. */
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void XPROGTarget_DisableTargetPDI(void)
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{
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#if defined(XPROG_VIA_HARDWARE_USART)
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/* Turn off receiver and transmitter of the USART, clear settings */
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UCSR1A |= (1 << TXC1) | (1 << RXC1);
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UCSR1B = 0;
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UCSR1C = 0;
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/* Set all USART lines as input, tristate */
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DDRD &= ~((1 << 5) | (1 << 3));
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PORTD &= ~((1 << 5) | (1 << 3) | (1 << 2));
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#else
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/* Set DATA and CLOCK lines to inputs */
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BITBANG_PDIDATA_DDR &= ~BITBANG_PDIDATA_MASK;
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BITBANG_PDICLOCK_DDR &= ~BITBANG_PDICLOCK_MASK;
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/* Tristate DATA and CLOCK lines */
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BITBANG_PDIDATA_PORT &= ~BITBANG_PDIDATA_MASK;
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BITBANG_PDICLOCK_PORT &= ~BITBANG_PDICLOCK_MASK;
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#endif
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}
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/** Sends a byte via the USART.
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*
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* \param[in] Byte Byte to send through the USART
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@ -56,7 +56,29 @@
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/* Defines: */
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#if ((BOARD == BOARD_XPLAIN) || (BOARD == BOARD_XPLAIN_REV1))
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#define XPROG_VIA_HARDWARE_USART
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// #define XPROG_VIA_HARDWARE_USART
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#define BITBANG_PDIDATA_PORT PORTD
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#define BITBANG_PDIDATA_DDR DDRD
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#define BITBANG_PDIDATA_PIN PIND
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#define BITBANG_PDIDATA_MASK (1 << 3)
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#define BITBANG_PDICLOCK_PORT PORTD
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#define BITBANG_PDICLOCK_DDR DDRD
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#define BITBANG_PDICLOCK_PIN PIND
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#define BITBANG_PDICLOCK_MASK (1 << 5)
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#define BITBANG_TPIDATA_PORT PORTB
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#define BITBANG_TPIDATA_DDR DDRB
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#define BITBANG_TPIDATA_PIN PINB
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#define BITBANG_TPIDATA_MASK (1 << 3)
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#define BITBANG_TPICLOCK_PORT PORTB
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#define BITBANG_TPICLOCK_DDR DDRB
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#define BITBANG_TPICLOCK_PIN PINB
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#define BITBANG_TPICLOCK_MASK (1 << 1)
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#else
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#define BITBANG_PDIDATA_PORT PORTB
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#define BITBANG_PDIDATA_DDR DDRB
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#define TPI_POINTER_INDIRECT_PI (1 << 2)
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/* Function Prototypes: */
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void XPROGTarget_EnableTargetTPI(void);
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void XPROGTarget_EnableTargetPDI(void);
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void XPROGTarget_DisableTargetTPI(void);
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void XPROGTarget_EnableTargetTPI(void);
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void XPROGTarget_DisableTargetPDI(void);
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void XPROGTarget_DisableTargetTPI(void);
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void XPROGTarget_SendByte(const uint8_t Byte);
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uint8_t XPROGTarget_ReceiveByte(void);
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void XPROGTarget_SendBreak(void);
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@ -60,7 +60,7 @@
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# MCU name
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MCU = at90usb162
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MCU = at90usb1287
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# Target board (see library "Board Types" documentation, USER or blank for projects not requiring
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