forked from mfulz_github/qmk_firmware
Refactor AVRISP MKII Clone PDI/TPI command constants to simplify the driver code.
This commit is contained in:
parent
e1b19e4e10
commit
560e5f75fb
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@ -55,8 +55,8 @@ static void TINYNVM_SendPointerAddress(const uint16_t AbsoluteAddress)
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static void TINYNVM_SendReadNVMRegister(const uint8_t Address)
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{
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/* The TPI command for reading from the I/O space uses strange addressing, where the I/O address's upper
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* two bits of the 6-bit address are shifted left once */
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XPROGTarget_SendByte(TPI_CMD_SIN | ((Address & 0x30) << 1) | (Address & 0x0F));
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* two bits of the 6-bit address are shifted left once - use function to reduce code size */
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XPROGTarget_SendByte(TPI_CMD_SIN(Address));
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}
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/** Sends a SOUT command to the target with the specified I/O address, ready for the data byte to be read.
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@ -66,8 +66,8 @@ static void TINYNVM_SendReadNVMRegister(const uint8_t Address)
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static void TINYNVM_SendWriteNVMRegister(const uint8_t Address)
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{
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/* The TPI command for reading from the I/O space uses strange addressing, where the I/O address's upper
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* two bits of the 6-bit address are shifted left once */
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XPROGTarget_SendByte(TPI_CMD_SOUT | ((Address & 0x30) << 1) | (Address & 0x0F));
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* two bits of the 6-bit address are shifted left once - use function to reduce code size */
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XPROGTarget_SendByte(TPI_CMD_SOUT(Address));
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}
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/** Busy-waits while the NVM controller is busy performing a NVM operation, such as a FLASH page read.
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@ -80,7 +80,7 @@ bool TINYNVM_WaitWhileNVMBusBusy(void)
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for (;;)
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{
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/* Send the SLDCS command to read the TPI STATUS register to see the NVM bus is active */
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XPROGTarget_SendByte(TPI_CMD_SLDCS | TPI_STATUS_REG);
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XPROGTarget_SendByte(TPI_CMD_SLDCS(TPI_REG_STATUS));
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uint8_t StatusRegister = XPROGTarget_ReceiveByte();
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@ -129,7 +129,7 @@ bool TINYNVM_EnableTPI(void)
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XPROGTarget_EnableTargetTPI();
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/* Lower direction change guard time to 32 USART bits */
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XPROGTarget_SendByte(TPI_CMD_SSTCS | TPI_CTRL_REG);
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XPROGTarget_SendByte(TPI_CMD_SSTCS(TPI_REG_CTRL));
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XPROGTarget_SendByte(0x02);
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/* Enable access to the XPROG NVM bus by sending the documented NVM access key to the device */
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@ -149,11 +149,11 @@ void TINYNVM_DisableTPI(void)
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do
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{
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/* Clear the NVMEN bit in the TPI STATUS register to disable TPI mode */
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XPROGTarget_SendByte(TPI_CMD_SSTCS | TPI_STATUS_REG);
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XPROGTarget_SendByte(TPI_CMD_SSTCS(TPI_REG_STATUS));
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XPROGTarget_SendByte(0x00);
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/* Read back the STATUS register, check to see if it took effect */
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XPROGTarget_SendByte(TPI_CMD_SLDCS | PDI_RESET_REG);
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XPROGTarget_SendByte(TPI_CMD_SLDCS(TPI_REG_STATUS));
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} while (XPROGTarget_ReceiveByte() != 0x00);
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XPROGTarget_DisableTargetTPI();
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@ -185,7 +185,7 @@ bool TINYNVM_ReadMemory(const uint16_t ReadAddress,
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while (ReadSize-- && TimeoutTicksRemaining)
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{
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/* Read the byte of data from the target */
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XPROGTarget_SendByte(TPI_CMD_SLD | TPI_POINTER_INDIRECT_PI);
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XPROGTarget_SendByte(TPI_CMD_SLD(TPI_POINTER_INDIRECT_PI));
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*(ReadBuffer++) = XPROGTarget_ReceiveByte();
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}
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@ -226,11 +226,11 @@ bool TINYNVM_WriteMemory(const uint16_t WriteAddress,
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return false;
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/* Write the low byte of data to the target */
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XPROGTarget_SendByte(TPI_CMD_SST | TPI_POINTER_INDIRECT_PI);
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XPROGTarget_SendByte(TPI_CMD_SST(TPI_POINTER_INDIRECT_PI));
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XPROGTarget_SendByte(*(WriteBuffer++));
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/* Write the high byte of data to the target */
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XPROGTarget_SendByte(TPI_CMD_SST | TPI_POINTER_INDIRECT_PI);
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XPROGTarget_SendByte(TPI_CMD_SST(TPI_POINTER_INDIRECT_PI));
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XPROGTarget_SendByte(*(WriteBuffer++));
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/* Need to decrement the write length twice, since we wrote a whole two-byte word */
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@ -260,7 +260,7 @@ bool TINYNVM_EraseMemory(const uint8_t EraseCommand,
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/* Write to a high byte location within the target address space to start the erase process */
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TINYNVM_SendPointerAddress(Address | 0x0001);
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XPROGTarget_SendByte(TPI_CMD_SST | TPI_POINTER_INDIRECT);
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XPROGTarget_SendByte(TPI_CMD_SST(TPI_POINTER_INDIRECT));
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XPROGTarget_SendByte(0x00);
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/* Wait until the NVM controller is no longer busy */
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@ -75,7 +75,7 @@ bool XMEGANVM_WaitWhileNVMBusBusy(void)
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for (;;)
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{
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/* Send the LDCS command to read the PDI STATUS register to see the NVM bus is active */
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XPROGTarget_SendByte(PDI_CMD_LDCS | PDI_STATUS_REG);
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XPROGTarget_SendByte(PDI_CMD_LDCS(PDI_REG_STATUS));
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uint8_t StatusRegister = XPROGTarget_ReceiveByte();
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@ -97,14 +97,14 @@ bool XMEGANVM_WaitWhileNVMBusBusy(void)
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bool XMEGANVM_WaitWhileNVMControllerBusy(void)
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{
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/* Preload the pointer register with the NVM STATUS register address to check the BUSY flag */
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XPROGTarget_SendByte(PDI_CMD_ST | (PDI_POINTER_DIRECT << 2) | PDI_DATSIZE_4BYTES);
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XPROGTarget_SendByte(PDI_CMD_ST(PDI_POINTER_DIRECT, PDI_DATSIZE_4BYTES));
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XMEGANVM_SendNVMRegAddress(XMEGA_NVM_REG_STATUS);
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/* Poll the NVM STATUS register while the NVM controller is busy */
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for (;;)
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{
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/* Fetch the current status value via the pointer register (without auto-increment afterwards) */
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XPROGTarget_SendByte(PDI_CMD_LD | (PDI_POINTER_INDIRECT << 2) | PDI_DATSIZE_1BYTE);
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XPROGTarget_SendByte(PDI_CMD_LD(PDI_POINTER_INDIRECT, PDI_DATSIZE_1BYTE));
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uint8_t StatusRegister = XPROGTarget_ReceiveByte();
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@ -128,11 +128,11 @@ bool XMEGANVM_EnablePDI(void)
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XPROGTarget_EnableTargetPDI();
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/* Store the RESET key into the RESET PDI register to keep the XMEGA in reset */
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XPROGTarget_SendByte(PDI_CMD_STCS | PDI_RESET_REG);
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XPROGTarget_SendByte(PDI_CMD_STCS(PDI_REG_RESET));
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XPROGTarget_SendByte(PDI_RESET_KEY);
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/* Lower direction change guard time to 32 USART bits */
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XPROGTarget_SendByte(PDI_CMD_STCS | PDI_CTRL_REG);
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XPROGTarget_SendByte(PDI_CMD_STCS(PDI_REG_CTRL));
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XPROGTarget_SendByte(0x02);
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/* Enable access to the XPROG NVM bus by sending the documented NVM access key to the device */
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@ -155,11 +155,11 @@ void XMEGANVM_DisablePDI(void)
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do
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{
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/* Clear reset register */
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XPROGTarget_SendByte(PDI_CMD_STCS | PDI_RESET_REG);
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XPROGTarget_SendByte(PDI_CMD_STCS(PDI_REG_RESET));
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XPROGTarget_SendByte(0x00);
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/* Read back the reset register, check to see if it took effect */
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XPROGTarget_SendByte(PDI_CMD_LDCS | PDI_RESET_REG);
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XPROGTarget_SendByte(PDI_CMD_LDCS(PDI_REG_RESET));
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} while (XPROGTarget_ReceiveByte() != 0x00);
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XPROGTarget_DisableTargetPDI();
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@ -182,12 +182,12 @@ bool XMEGANVM_GetMemoryCRC(const uint8_t CRCCommand,
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return false;
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/* Set the NVM command to the correct CRC read command */
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XPROGTarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));
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XPROGTarget_SendByte(PDI_CMD_STS(PDI_DATSIZE_4BYTES, PDI_DATSIZE_1BYTE));
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XMEGANVM_SendNVMRegAddress(XMEGA_NVM_REG_CMD);
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XPROGTarget_SendByte(CRCCommand);
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/* Set CMDEX bit in NVM CTRLA register to start the CRC generation */
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XPROGTarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));
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XPROGTarget_SendByte(PDI_CMD_STS(PDI_DATSIZE_4BYTES, PDI_DATSIZE_1BYTE));
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XMEGANVM_SendNVMRegAddress(XMEGA_NVM_REG_CTRLA);
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XPROGTarget_SendByte(XMEGA_NVM_BIT_CTRLA_CMDEX);
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@ -200,15 +200,15 @@ bool XMEGANVM_GetMemoryCRC(const uint8_t CRCCommand,
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return false;
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/* Load the PDI pointer register with the DAT0 register start address */
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XPROGTarget_SendByte(PDI_CMD_ST | (PDI_POINTER_DIRECT << 2) | PDI_DATSIZE_4BYTES);
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XPROGTarget_SendByte(PDI_CMD_ST(PDI_POINTER_DIRECT, PDI_DATSIZE_4BYTES));
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XMEGANVM_SendNVMRegAddress(XMEGA_NVM_REG_DAT0);
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/* Send the REPEAT command to grab the CRC bytes */
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XPROGTarget_SendByte(PDI_CMD_REPEAT | PDI_DATSIZE_1BYTE);
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XPROGTarget_SendByte(PDI_CMD_REPEAT(PDI_DATSIZE_1BYTE));
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XPROGTarget_SendByte(XMEGA_CRC_LENGTH_BYTES - 1);
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/* Read in the CRC bytes from the target */
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XPROGTarget_SendByte(PDI_CMD_LD | (PDI_POINTER_INDIRECT_PI << 2) | PDI_DATSIZE_1BYTE);
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XPROGTarget_SendByte(PDI_CMD_LD(PDI_POINTER_INDIRECT_PI, PDI_DATSIZE_1BYTE));
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for (uint8_t i = 0; i < XMEGA_CRC_LENGTH_BYTES; i++)
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((uint8_t*)CRCDest)[i] = XPROGTarget_ReceiveByte();
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@ -232,29 +232,29 @@ bool XMEGANVM_ReadMemory(const uint32_t ReadAddress,
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return false;
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/* Send the READNVM command to the NVM controller for reading of an arbitrary location */
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XPROGTarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));
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XPROGTarget_SendByte(PDI_CMD_STS(PDI_DATSIZE_4BYTES, PDI_DATSIZE_1BYTE));
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XMEGANVM_SendNVMRegAddress(XMEGA_NVM_REG_CMD);
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XPROGTarget_SendByte(XMEGA_NVM_CMD_READNVM);
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if (ReadSize > 1)
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{
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/* Load the PDI pointer register with the start address we want to read from */
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XPROGTarget_SendByte(PDI_CMD_ST | (PDI_POINTER_DIRECT << 2) | PDI_DATSIZE_4BYTES);
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XPROGTarget_SendByte(PDI_CMD_ST(PDI_POINTER_DIRECT, PDI_DATSIZE_4BYTES));
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XMEGANVM_SendAddress(ReadAddress);
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/* Send the REPEAT command with the specified number of bytes to read */
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XPROGTarget_SendByte(PDI_CMD_REPEAT | PDI_DATSIZE_1BYTE);
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XPROGTarget_SendByte(PDI_CMD_REPEAT(PDI_DATSIZE_1BYTE));
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XPROGTarget_SendByte(ReadSize - 1);
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/* Send a LD command with indirect access and post-increment to read out the bytes */
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XPROGTarget_SendByte(PDI_CMD_LD | (PDI_POINTER_INDIRECT_PI << 2) | PDI_DATSIZE_1BYTE);
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XPROGTarget_SendByte(PDI_CMD_LD(PDI_POINTER_INDIRECT_PI, PDI_DATSIZE_1BYTE));
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while (ReadSize-- && TimeoutTicksRemaining)
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*(ReadBuffer++) = XPROGTarget_ReceiveByte();
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}
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else
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{
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/* Send a LDS command with the read address to read out the requested byte */
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XPROGTarget_SendByte(PDI_CMD_LDS | (PDI_DATSIZE_4BYTES << 2));
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XPROGTarget_SendByte(PDI_CMD_LDS(PDI_DATSIZE_4BYTES, PDI_DATSIZE_1BYTE));
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XMEGANVM_SendAddress(ReadAddress);
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*(ReadBuffer++) = XPROGTarget_ReceiveByte();
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}
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@ -279,12 +279,12 @@ bool XMEGANVM_WriteByteMemory(const uint8_t WriteCommand,
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return false;
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/* Send the memory write command to the target */
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XPROGTarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));
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XPROGTarget_SendByte(PDI_CMD_STS(PDI_DATSIZE_4BYTES, PDI_DATSIZE_1BYTE));
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XMEGANVM_SendNVMRegAddress(XMEGA_NVM_REG_CMD);
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XPROGTarget_SendByte(WriteCommand);
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/* Send new memory byte to the memory of the target */
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XPROGTarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));
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XPROGTarget_SendByte(PDI_CMD_STS(PDI_DATSIZE_4BYTES, PDI_DATSIZE_1BYTE));
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XMEGANVM_SendAddress(WriteAddress);
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XPROGTarget_SendByte(Byte);
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@ -318,12 +318,12 @@ bool XMEGANVM_WritePageMemory(const uint8_t WriteBuffCommand,
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return false;
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/* Send the memory buffer erase command to the target */
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XPROGTarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));
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XPROGTarget_SendByte(PDI_CMD_STS(PDI_DATSIZE_4BYTES, PDI_DATSIZE_1BYTE));
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XMEGANVM_SendNVMRegAddress(XMEGA_NVM_REG_CMD);
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XPROGTarget_SendByte(EraseBuffCommand);
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/* Set CMDEX bit in NVM CTRLA register to start the buffer erase */
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XPROGTarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));
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XPROGTarget_SendByte(PDI_CMD_STS(PDI_DATSIZE_4BYTES, PDI_DATSIZE_1BYTE));
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XMEGANVM_SendNVMRegAddress(XMEGA_NVM_REG_CTRLA);
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XPROGTarget_SendByte(XMEGA_NVM_BIT_CTRLA_CMDEX);
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}
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@ -335,20 +335,20 @@ bool XMEGANVM_WritePageMemory(const uint8_t WriteBuffCommand,
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return false;
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/* Send the memory buffer write command to the target */
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XPROGTarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));
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XPROGTarget_SendByte(PDI_CMD_STS(PDI_DATSIZE_4BYTES, PDI_DATSIZE_1BYTE));
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XMEGANVM_SendNVMRegAddress(XMEGA_NVM_REG_CMD);
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XPROGTarget_SendByte(WriteBuffCommand);
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/* Load the PDI pointer register with the start address we want to write to */
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XPROGTarget_SendByte(PDI_CMD_ST | (PDI_POINTER_DIRECT << 2) | PDI_DATSIZE_4BYTES);
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XPROGTarget_SendByte(PDI_CMD_ST(PDI_POINTER_DIRECT, PDI_DATSIZE_4BYTES));
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XMEGANVM_SendAddress(WriteAddress);
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/* Send the REPEAT command with the specified number of bytes to write */
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XPROGTarget_SendByte(PDI_CMD_REPEAT | PDI_DATSIZE_1BYTE);
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XPROGTarget_SendByte(PDI_CMD_REPEAT(PDI_DATSIZE_1BYTE));
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XPROGTarget_SendByte(WriteSize - 1);
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/* Send a ST command with indirect access and post-increment to write the bytes */
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XPROGTarget_SendByte(PDI_CMD_ST | (PDI_POINTER_INDIRECT_PI << 2) | PDI_DATSIZE_1BYTE);
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XPROGTarget_SendByte(PDI_CMD_ST(PDI_POINTER_INDIRECT_PI, PDI_DATSIZE_1BYTE));
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while (WriteSize--)
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XPROGTarget_SendByte(*(WriteBuffer++));
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}
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@ -360,12 +360,12 @@ bool XMEGANVM_WritePageMemory(const uint8_t WriteBuffCommand,
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return false;
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/* Send the memory write command to the target */
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XPROGTarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));
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XPROGTarget_SendByte(PDI_CMD_STS(PDI_DATSIZE_4BYTES, PDI_DATSIZE_1BYTE));
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XMEGANVM_SendNVMRegAddress(XMEGA_NVM_REG_CMD);
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XPROGTarget_SendByte(WritePageCommand);
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/* Send the address of the first page location to write the memory page */
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XPROGTarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));
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XPROGTarget_SendByte(PDI_CMD_STS(PDI_DATSIZE_4BYTES, PDI_DATSIZE_1BYTE));
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XMEGANVM_SendAddress(WriteAddress);
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XPROGTarget_SendByte(0x00);
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}
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@ -391,24 +391,24 @@ bool XMEGANVM_EraseMemory(const uint8_t EraseCommand,
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if (EraseCommand == XMEGA_NVM_CMD_CHIPERASE)
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{
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/* Send the memory erase command to the target */
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XPROGTarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));
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XPROGTarget_SendByte(PDI_CMD_STS(PDI_DATSIZE_4BYTES, PDI_DATSIZE_1BYTE));
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XMEGANVM_SendNVMRegAddress(XMEGA_NVM_REG_CMD);
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XPROGTarget_SendByte(EraseCommand);
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/* Set CMDEX bit in NVM CTRLA register to start the erase sequence */
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XPROGTarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));
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XPROGTarget_SendByte(PDI_CMD_STS(PDI_DATSIZE_4BYTES, PDI_DATSIZE_1BYTE));
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XMEGANVM_SendNVMRegAddress(XMEGA_NVM_REG_CTRLA);
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XPROGTarget_SendByte(XMEGA_NVM_BIT_CTRLA_CMDEX);
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}
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else if (EraseCommand == XMEGA_NVM_CMD_ERASEEEPROM)
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{
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/* Send the EEPROM page buffer erase command to the target */
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XPROGTarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));
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XPROGTarget_SendByte(PDI_CMD_STS(PDI_DATSIZE_4BYTES, PDI_DATSIZE_1BYTE));
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XMEGANVM_SendNVMRegAddress(XMEGA_NVM_REG_CMD);
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XPROGTarget_SendByte(XMEGA_NVM_CMD_ERASEEEPROMPAGEBUFF);
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/* Set CMDEX bit in NVM CTRLA register to start the buffer erase */
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XPROGTarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));
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XPROGTarget_SendByte(PDI_CMD_STS(PDI_DATSIZE_4BYTES, PDI_DATSIZE_1BYTE));
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XMEGANVM_SendNVMRegAddress(XMEGA_NVM_REG_CTRLA);
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XPROGTarget_SendByte(XMEGA_NVM_BIT_CTRLA_CMDEX);
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@ -417,42 +417,42 @@ bool XMEGANVM_EraseMemory(const uint8_t EraseCommand,
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return false;
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/* Send the EEPROM memory buffer write command to the target */
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XPROGTarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));
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XPROGTarget_SendByte(PDI_CMD_STS(PDI_DATSIZE_4BYTES, PDI_DATSIZE_1BYTE));
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XMEGANVM_SendNVMRegAddress(XMEGA_NVM_REG_CMD);
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XPROGTarget_SendByte(XMEGA_NVM_CMD_LOADEEPROMPAGEBUFF);
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/* Load the PDI pointer register with the EEPROM page start address */
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XPROGTarget_SendByte(PDI_CMD_ST | (PDI_POINTER_DIRECT << 2) | PDI_DATSIZE_4BYTES);
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XPROGTarget_SendByte(PDI_CMD_ST(PDI_POINTER_DIRECT, PDI_DATSIZE_4BYTES));
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XMEGANVM_SendAddress(Address);
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/* Send the REPEAT command with the specified number of bytes to write */
|
||||
XPROGTarget_SendByte(PDI_CMD_REPEAT | PDI_DATSIZE_1BYTE);
|
||||
XPROGTarget_SendByte(PDI_CMD_REPEAT(PDI_DATSIZE_1BYTE));
|
||||
XPROGTarget_SendByte(XPROG_Param_EEPageSize - 1);
|
||||
|
||||
/* Send a ST command with indirect access and post-increment to tag each byte in the EEPROM page buffer */
|
||||
XPROGTarget_SendByte(PDI_CMD_ST | (PDI_POINTER_INDIRECT_PI << 2) | PDI_DATSIZE_1BYTE);
|
||||
XPROGTarget_SendByte(PDI_CMD_ST(PDI_POINTER_INDIRECT_PI, PDI_DATSIZE_1BYTE));
|
||||
for (uint8_t PageByte = 0; PageByte < XPROG_Param_EEPageSize; PageByte++)
|
||||
XPROGTarget_SendByte(0x00);
|
||||
|
||||
/* Send the memory erase command to the target */
|
||||
XPROGTarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));
|
||||
XPROGTarget_SendByte(PDI_CMD_STS(PDI_DATSIZE_4BYTES, PDI_DATSIZE_1BYTE));
|
||||
XMEGANVM_SendNVMRegAddress(XMEGA_NVM_REG_CMD);
|
||||
XPROGTarget_SendByte(EraseCommand);
|
||||
|
||||
/* Set CMDEX bit in NVM CTRLA register to start the EEPROM erase sequence */
|
||||
XPROGTarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));
|
||||
XPROGTarget_SendByte(PDI_CMD_STS(PDI_DATSIZE_4BYTES, PDI_DATSIZE_1BYTE));
|
||||
XMEGANVM_SendNVMRegAddress(XMEGA_NVM_REG_CTRLA);
|
||||
XPROGTarget_SendByte(XMEGA_NVM_BIT_CTRLA_CMDEX);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Send the memory erase command to the target */
|
||||
XPROGTarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));
|
||||
XPROGTarget_SendByte(PDI_CMD_STS(PDI_DATSIZE_4BYTES, PDI_DATSIZE_1BYTE));
|
||||
XMEGANVM_SendNVMRegAddress(XMEGA_NVM_REG_CMD);
|
||||
XPROGTarget_SendByte(EraseCommand);
|
||||
|
||||
/* Other erase modes just need us to address a byte within the target memory space */
|
||||
XPROGTarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));
|
||||
XPROGTarget_SendByte(PDI_CMD_STS(PDI_DATSIZE_4BYTES, PDI_DATSIZE_1BYTE));
|
||||
XMEGANVM_SendAddress(Address);
|
||||
XPROGTarget_SendByte(0x00);
|
||||
}
|
||||
|
|
|
@ -62,18 +62,21 @@
|
|||
/** Total number of bits in a single USART frame. */
|
||||
#define BITS_IN_USART_FRAME 12
|
||||
|
||||
#define PDI_CMD_LDS 0x00
|
||||
#define PDI_CMD_LD 0x20
|
||||
#define PDI_CMD_STS 0x40
|
||||
#define PDI_CMD_ST 0x60
|
||||
#define PDI_CMD_LDCS 0x80
|
||||
#define PDI_CMD_REPEAT 0xA0
|
||||
#define PDI_CMD_STCS 0xC0
|
||||
#define PDI_CMD_KEY 0xE0
|
||||
/** \name PDI Related Constants
|
||||
* @{
|
||||
*/
|
||||
#define PDI_CMD_LDS(AddressSize, DataSize) (0x00 | ( AddressSize << 2) | DataSize)
|
||||
#define PDI_CMD_LD(PointerAccess, DataSize) (0x20 | (PointerAccess << 2) | DataSize)
|
||||
#define PDI_CMD_STS(AddressSize, DataSize) (0x40 | ( AddressSize << 2) | DataSize)
|
||||
#define PDI_CMD_ST(PointerAccess, DataSize) (0x60 | (PointerAccess << 2) | DataSize)
|
||||
#define PDI_CMD_LDCS(PDIReg) (0x80 | PDIReg)
|
||||
#define PDI_CMD_REPEAT(DataSize) (0xA0 | DataSize)
|
||||
#define PDI_CMD_STCS(PDIReg) (0xC0 | PDIReg)
|
||||
#define PDI_CMD_KEY 0xE0
|
||||
|
||||
#define PDI_STATUS_REG 0
|
||||
#define PDI_RESET_REG 1
|
||||
#define PDI_CTRL_REG 2
|
||||
#define PDI_REG_STATUS 0
|
||||
#define PDI_REG_RESET 1
|
||||
#define PDI_REG_CTRL 2
|
||||
|
||||
#define PDI_STATUS_NVM (1 << 1)
|
||||
|
||||
|
@ -88,19 +91,23 @@
|
|||
#define PDI_POINTER_INDIRECT 0
|
||||
#define PDI_POINTER_INDIRECT_PI 1
|
||||
#define PDI_POINTER_DIRECT 2
|
||||
/** @} */
|
||||
|
||||
#define TPI_CMD_SLD 0x20
|
||||
#define TPI_CMD_SST 0x60
|
||||
/** \name TPI Related Constants
|
||||
* @{
|
||||
*/
|
||||
#define TPI_CMD_SLD(PointerAccess) (0x20 | PointerAccess)
|
||||
#define TPI_CMD_SST(PointerAccess) (0x60 | PointerAccess)
|
||||
#define TPI_CMD_SSTPR 0x68
|
||||
#define TPI_CMD_SIN 0x10
|
||||
#define TPI_CMD_SOUT 0x90
|
||||
#define TPI_CMD_SLDCS 0x80
|
||||
#define TPI_CMD_SSTCS 0xC0
|
||||
#define TPI_CMD_SIN(Address) (0x10 | ((Address & 0x30) << 1) | (Address & 0x0F))
|
||||
#define TPI_CMD_SOUT(Address) (0x90 | ((Address & 0x30) << 1) | (Address & 0x0F))
|
||||
#define TPI_CMD_SLDCS(TPIReg) (0x80 | TPIReg)
|
||||
#define TPI_CMD_SSTCS(TPIReg) (0xC0 | TPIReg)
|
||||
#define TPI_CMD_SKEY 0xE0
|
||||
|
||||
#define TPI_STATUS_REG 0x00
|
||||
#define TPI_CTRL_REG 0x02
|
||||
#define TPI_ID_REG 0x0F
|
||||
#define TPI_REG_STATUS 0x00
|
||||
#define TPI_REG_CTRL 0x02
|
||||
#define TPI_REG_ID 0x0F
|
||||
|
||||
#define TPI_STATUS_NVM (1 << 1)
|
||||
|
||||
|
@ -108,6 +115,7 @@
|
|||
|
||||
#define TPI_POINTER_INDIRECT 0
|
||||
#define TPI_POINTER_INDIRECT_PI 4
|
||||
/** @} */
|
||||
|
||||
/* Function Prototypes: */
|
||||
void XPROGTarget_EnableTargetPDI(void);
|
||||
|
|
Loading…
Reference in New Issue