forked from mfulz_github/qmk_firmware
Add Lock/Fuse byte programming support to the AVRISP PDI programming protocol code.
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@ -114,6 +114,10 @@ bool NVMTarget_GetMemoryCRC(uint8_t CRCCommand, uint32_t* CRCDest)
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NVMTarget_SendNVMRegAddress(NVM_REG_CTRLA);
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NVMTarget_SendNVMRegAddress(NVM_REG_CTRLA);
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PDITarget_SendByte(1 << 0);
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PDITarget_SendByte(1 << 0);
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/* Wait until the NVM bus is ready again */
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if (!(PDITarget_WaitWhileNVMBusBusy()))
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return false;
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/* Wait until the NVM controller is no longer busy */
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/* Wait until the NVM controller is no longer busy */
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if (!(NVMTarget_WaitWhileNVMControllerBusy()))
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if (!(NVMTarget_WaitWhileNVMControllerBusy()))
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return false;
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return false;
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@ -180,6 +184,37 @@ bool NVMTarget_ReadMemory(uint32_t ReadAddress, uint8_t* ReadBuffer, uint16_t Re
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return true;
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return true;
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}
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}
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/** Writes byte addressed memory to the target's memory spaces.
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*
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* \param[in] WriteCommand Command to send to the device to write each memory page
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* \param[in] WriteAddress Start address to write to within the target's address space
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* \param[in] WriteBuffer Buffer to source data from
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* \param[in] WriteSize Number of bytes to write
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*
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* \return Boolean true if the command sequence complete sucessfully
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*/
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bool NVMTarget_WriteByteMemory(uint8_t WriteCommand, uint32_t WriteAddress, uint8_t* WriteBuffer, uint16_t WriteSize)
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{
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for (uint8_t i = 0; i < WriteSize; i++)
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{
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/* Wait until the NVM controller is no longer busy */
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if (!(NVMTarget_WaitWhileNVMControllerBusy()))
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return false;
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/* Send the memory write command to the target */
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PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));
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NVMTarget_SendNVMRegAddress(NVM_REG_CMD);
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PDITarget_SendByte(WriteCommand);
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/* Send each new memory byte to the memory to the target */
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PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));
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NVMTarget_SendAddress(WriteAddress++);
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PDITarget_SendByte(*(WriteBuffer++));
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}
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return true;
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}
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/** Erases a specific memory space of the target.
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/** Erases a specific memory space of the target.
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*
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*
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* \param[in] EraseCommand NVM erase command to send to the device
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* \param[in] EraseCommand NVM erase command to send to the device
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@ -111,6 +111,8 @@
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bool NVMTarget_WaitWhileNVMControllerBusy(void);
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bool NVMTarget_WaitWhileNVMControllerBusy(void);
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bool NVMTarget_GetMemoryCRC(uint8_t CRCCommand, uint32_t* CRCDest);
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bool NVMTarget_GetMemoryCRC(uint8_t CRCCommand, uint32_t* CRCDest);
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bool NVMTarget_ReadMemory(uint32_t ReadAddress, uint8_t* ReadBuffer, uint16_t ReadSize);
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bool NVMTarget_ReadMemory(uint32_t ReadAddress, uint8_t* ReadBuffer, uint16_t ReadSize);
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bool NVMTarget_WriteByteMemory(uint8_t WriteCommand, uint32_t WriteAddress, uint8_t* WriteBuffer,
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uint16_t WriteSize);
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bool NVMTarget_EraseMemory(uint8_t EraseCommand, uint32_t Address);
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bool NVMTarget_EraseMemory(uint8_t EraseCommand, uint32_t Address);
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#endif
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#endif
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@ -162,7 +162,7 @@ static void PDIProtocol_Erase(void)
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Endpoint_ClearOUT();
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Endpoint_ClearOUT();
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Endpoint_SetEndpointDirection(ENDPOINT_DIR_IN);
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Endpoint_SetEndpointDirection(ENDPOINT_DIR_IN);
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uint8_t EraseCommand;
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uint8_t EraseCommand = NVM_CMD_NOOP;
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if (Erase_XPROG_Params.MemoryType == XPRG_ERASE_CHIP)
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if (Erase_XPROG_Params.MemoryType == XPRG_ERASE_CHIP)
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EraseCommand = NVM_CMD_CHIPERASE;
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EraseCommand = NVM_CMD_CHIPERASE;
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@ -198,9 +198,10 @@ static void PDIProtocol_WriteMemory(void)
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struct
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struct
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{
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{
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uint8_t MemoryType;
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uint8_t MemoryType;
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uint8_t PageMode;
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uint32_t Address;
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uint32_t Address;
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uint16_t Length;
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uint16_t Length;
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uint8_t ProgData[256];
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uint8_t ProgData[512];
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} WriteMemory_XPROG_Params;
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} WriteMemory_XPROG_Params;
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Endpoint_Read_Stream_LE(&WriteMemory_XPROG_Params, (sizeof(WriteMemory_XPROG_Params) -
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Endpoint_Read_Stream_LE(&WriteMemory_XPROG_Params, (sizeof(WriteMemory_XPROG_Params) -
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@ -212,10 +213,51 @@ static void PDIProtocol_WriteMemory(void)
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Endpoint_ClearOUT();
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Endpoint_ClearOUT();
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Endpoint_SetEndpointDirection(ENDPOINT_DIR_IN);
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Endpoint_SetEndpointDirection(ENDPOINT_DIR_IN);
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// TODO: Send program command here via PDI protocol
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uint8_t WriteCommand = NVM_CMD_NOOP;
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uint8_t WritePageCommand = NVM_CMD_NOOP;
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bool PagedMemory = false;
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if (WriteMemory_XPROG_Params.MemoryType == XPRG_MEM_TYPE_APPL)
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{
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PagedMemory = true;
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}
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else if (WriteMemory_XPROG_Params.MemoryType == XPRG_MEM_TYPE_BOOT)
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{
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PagedMemory = true;
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}
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else if (WriteMemory_XPROG_Params.MemoryType == XPRG_MEM_TYPE_EEPROM)
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{
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PagedMemory = true;
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}
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else if (WriteMemory_XPROG_Params.MemoryType == XPRG_MEM_TYPE_USERSIG)
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{
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PagedMemory = true;
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}
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else if (WriteMemory_XPROG_Params.MemoryType == XPRG_MEM_TYPE_FUSE)
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{
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WriteCommand = NVM_CMD_WRITEFUSE;
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}
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else if (WriteMemory_XPROG_Params.MemoryType == XPRG_MEM_TYPE_LOCKBITS)
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{
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WriteCommand = NVM_CMD_WRITELOCK;
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}
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if (PagedMemory)
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{
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}
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else
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{
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if (!(NVMTarget_WriteByteMemory(WriteCommand, WriteMemory_XPROG_Params.Address, WriteMemory_XPROG_Params.ProgData,
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WriteMemory_XPROG_Params.Length)))
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{
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ReturnStatus = XPRG_ERR_TIMEOUT;
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}
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}
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Endpoint_Write_Byte(CMD_XPROG);
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Endpoint_Write_Byte(CMD_XPROG);
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Endpoint_Write_Byte(XPRG_CMD_READ_MEM);
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Endpoint_Write_Byte(XPRG_CMD_WRITE_MEM);
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Endpoint_Write_Byte(ReturnStatus);
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Endpoint_Write_Byte(ReturnStatus);
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Endpoint_ClearIN();
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Endpoint_ClearIN();
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}
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}
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@ -272,8 +314,8 @@ static void PDIProtocol_ReadCRC(void)
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Endpoint_ClearOUT();
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Endpoint_ClearOUT();
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Endpoint_SetEndpointDirection(ENDPOINT_DIR_IN);
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Endpoint_SetEndpointDirection(ENDPOINT_DIR_IN);
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uint8_t CRCCommand = NVM_CMD_NOOP;
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uint32_t MemoryCRC;
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uint32_t MemoryCRC;
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uint8_t CRCCommand;
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if (ReadCRC_XPROG_Params.CRCType == XPRG_CRC_APP)
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if (ReadCRC_XPROG_Params.CRCType == XPRG_CRC_APP)
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CRCCommand = NVM_CMD_APPCRC;
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CRCCommand = NVM_CMD_APPCRC;
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