forked from mfulz_github/qmk_firmware
Removed software PDI/TPI emulation from the AVRISP-MKII clone project, as it was very buggy. PDI and TPI must now be implemented via seperate headers instead of the one unified ISP/TPI/PDI header.
This commit is contained in:
Dean Camera
parent
708a1c6166
commit
ab8668b14e
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@ -17,8 +17,7 @@
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* is suspended before or during a transfer
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*
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* <b>Changed:</b>
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* - AVRISP programmer project now has a more robust timeout system, allowing for an increase of the software USART speed
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* for PDI and TPI programming
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* - AVRISP programmer project now has a more robust timeout system
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* - Added a timeout value to the TWI_StartTransmission() function, within which the addressed device must respond
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* - Webserver project now uses the board LEDs to indicate the current IP configuration state
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* - Added ENABLE_TELNET_SERVER compile time option to the Webserver project to disable the TELNET server if desired
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@ -35,6 +34,8 @@
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* - The Audio_Device_IsSampleReceived() and Audio_Device_IsReadyForNextSample() functions are now inline, to reduce overhead
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* - Removed the cast to uint16_t on the set baud rate in the USBtoSerial project, so that the higher >1M baud rates can be
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* selected (thanks to Steffan Woltjer)
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* - Removed software PDI and TPI emulation from the AVRISP-MKII clone project as it was very buggy and slow - PDI and TPI must
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* now be implemented via seperate programming headers
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*
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* <b>Fixed:</b>
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* - Fixed software PDI/TPI programming mode in the AVRISP project not correctly toggling just the clock pin
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@ -56,17 +56,12 @@
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* Note that this design currently has the following limitations:
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* - Minimum ISP target clock speed of 500KHz due to hardware SPI module prescaler limitations
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* - No reversed/shorted target connector detection and notification
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* - Very slow TPI and PDI programming when in software emulated USART mode
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* - A seperate header is required for each of the ISP, PDI and TPI programming protocols that the user wishes to use
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*
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* On AVR models with an ADC converter, AVCC should be tied to 5V (e.g. VBUS) and the VTARGET_ADC_CHANNEL token should be
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* set to an appropriate ADC channel number in the project makefile for VTARGET detection to operate correctly. On models
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* without an ADC converter, VTARGET will report a fixed 5V level at all times.
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*
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* When compiled for the XPLAIN board target, this will automatically configure itself for the correct connections to the
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* XPLAIN's XMEGA AVR, and will enable hardware PDI/TPI only programming support (since ISP mode is not needed). Note that
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* the first revision XPLAIN board lacks a bootloader on the AT90USB1287, and thus for this firmware to be loaded, an external
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* programmer will be required.
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*
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* While this application can be compiled for USB AVRs with as little as 8KB of FLASH, for full functionality 16KB or more
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* of FLASH is required. On 8KB devices, ISP or PDI/TPI programming support can be disabled to reduce program size.
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*
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@ -128,7 +123,7 @@
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* <td><b>PDI 6 Pin Layout:</b></td>
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* </tr>
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* <tr>
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* <td>MISO <b><sup>2</sup></b></td>
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* <td>Tx/Rx <b><sup>2</sup></b></td>
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* <td>DATA</td>
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* <td>1</td>
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* </tr>
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@ -148,7 +143,7 @@
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* <td>4</td>
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* </tr>
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* <tr>
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* <td>PORTx.y <b><sup>2, 3</sup></b></td>
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* <td>XCLK</td>
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* <td>CLOCK</td>
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* <td>5</td>
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* </tr>
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@ -160,9 +155,7 @@
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* </table>
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*
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* <b><sup>1</sup></b> <i>Optional, see \ref SSec_Options section - for USB AVRs with ADC modules only</i> \n
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* <b><sup>2</sup></b> <i>When XPROG_VIA_HARDWARE_USART is set, the AVR's Tx and Rx become the DATA line when connected together
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* via a pair of 220 ohm resistors, and the AVR's XCK pin becomes CLOCK.</i> \n
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* <b><sup>3</sup></b> <i>See AUX line related tokens in the \ref SSec_Options section</i>
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* <b><sup>2</sup></b> <i>The AVR's Tx and Rx become the DATA line when connected together via a pair of 220 ohm resistors</i> \n
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*
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* \section Sec_TPI TPI Connections
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* Connections to the device for TPI programming<b><sup>1</sup></b> (when enabled):
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@ -174,7 +167,7 @@
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* <td><b>TPI 6 Pin Layout:</b></td>
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* </tr>
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* <tr>
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* <td>MISO <b><sup>2</sup></b></td>
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* <td>Tx/Rx <b><sup>2</sup></b></td>
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* <td>DATA</td>
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* <td>1</td>
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* </tr>
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@ -184,7 +177,7 @@
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* <td>2</td>
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* </tr>
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* <tr>
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* <td>SCLK <b><sup>2</sup></b></td>
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* <td>XCLK <b><sup>2</sup></b></td>
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* <td>CLOCK</td>
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* <td>3</td>
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* </tr>
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@ -206,8 +199,7 @@
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* </table>
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*
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* <b><sup>1</sup></b> <i>Optional, see \ref SSec_Options section - for USB AVRs with ADC modules only</i> \n
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* <b><sup>2</sup></b> <i>When XPROG_VIA_HARDWARE_USART is set, the AVR's Tx and Rx become the DATA line when connected together
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* via a pair of 220 ohm resistors, and the AVR's XCK pin becomes CLOCK.</i> \n
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* <b><sup>2</sup></b> <i>The AVR's Tx and Rx become the DATA line when connected together via a pair of 220 ohm resistors</i> \n
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* <b><sup>3</sup></b> <i>See AUX line related tokens in the \ref SSec_Options section</i>
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*
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* \section SSec_Options Project Options
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@ -261,14 +253,6 @@
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* <td>Define to enable PDI and TPI programming protocol support. <i>Ignored when compiled for the XPLAIN board.</i></td>
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* </tr>
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* <tr>
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* <td>XPROG_VIA_HARDWARE_USART</td>
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* <td>Makefile CDEFS</td>
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* <td>Define to force the PDI and TPI protocols (when enabled) to use the much faster hardware USART instead of bit-banging
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* to match the official AVRISP pinout. This breaks pinout compatibility with the official AVRISP MKII (and requires
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* seperate ISP, PDI, and TPI programming headers) but increases programming speed dramatically.
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* <i>Ignored when compiled for the XPLAIN board.</i></td>
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* </tr>
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* <tr>
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* <td>NO_VTARGET_DETECT</td>
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* <td>Makefile CDEFS</td>
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* <td>Define to disable VTARGET sampling and reporting on AVR models with an ADC converter. This will cause the programmer
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@ -39,115 +39,13 @@
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#if defined(ENABLE_XPROG_PROTOCOL) || defined(__DOXYGEN__)
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/** Flag to indicate if the USART is currently in Tx or Rx mode. */
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volatile bool IsSending;
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#if !defined(XPROG_VIA_HARDWARE_USART)
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/** Software USART raw frame bits for transmission/reception. */
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volatile uint16_t SoftUSART_Data;
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/** Bits remaining to be sent or received via the software USART - set as a GPIOR for speed. */
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#define SoftUSART_BitCount GPIOR2
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/** ISR to manage the PDI software USART when bit-banged PDI USART mode is selected. */
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ISR(TIMER1_COMPA_vect, ISR_BLOCK)
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{
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/* Toggle CLOCK pin in a single cycle (see AVR datasheet) */
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BITBANG_PDICLOCK_PIN = BITBANG_PDICLOCK_MASK;
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/* If not sending or receiving, just exit */
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if (!(SoftUSART_BitCount))
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return;
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/* Check to see if we are at a rising or falling edge of the clock */
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if (BITBANG_PDICLOCK_PORT & BITBANG_PDICLOCK_MASK)
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{
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/* If at rising clock edge and we are in send mode, abort */
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if (IsSending)
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return;
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/* Wait for the start bit when receiving */
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if ((SoftUSART_BitCount == BITS_IN_USART_FRAME) && (BITBANG_PDIDATA_PIN & BITBANG_PDIDATA_MASK))
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return;
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/* Shift in the bit one less than the frame size in position, so that the start bit will eventually
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* be discarded leaving the data to be byte-aligned for quick access (subtract 9 as we are ORing to the MSB) */
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if (BITBANG_PDIDATA_PIN & BITBANG_PDIDATA_MASK)
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((uint8_t*)&SoftUSART_Data)[1] |= (1 << (BITS_IN_USART_FRAME - 9));
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SoftUSART_Data >>= 1;
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SoftUSART_BitCount--;
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}
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else
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{
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/* If at falling clock edge and we are in receive mode, abort */
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if (!IsSending)
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return;
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/* Set the data line to the next bit value */
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if (((uint8_t*)&SoftUSART_Data)[0] & 0x01)
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BITBANG_PDIDATA_PORT |= BITBANG_PDIDATA_MASK;
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else
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BITBANG_PDIDATA_PORT &= ~BITBANG_PDIDATA_MASK;
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SoftUSART_Data >>= 1;
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SoftUSART_BitCount--;
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}
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}
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/** ISR to manage the TPI software USART when bit-banged TPI USART mode is selected. */
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ISR(TIMER1_CAPT_vect, ISR_BLOCK)
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{
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/* Toggle CLOCK pin in a single cycle (see AVR datasheet) */
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BITBANG_TPICLOCK_PIN = BITBANG_TPICLOCK_MASK;
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/* If not sending or receiving, just exit */
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if (!(SoftUSART_BitCount))
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return;
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/* Check to see if we are at a rising or falling edge of the clock */
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if (BITBANG_TPICLOCK_PORT & BITBANG_TPICLOCK_MASK)
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{
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/* If at rising clock edge and we are in send mode, abort */
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if (IsSending)
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return;
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/* Wait for the start bit when receiving */
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if ((SoftUSART_BitCount == BITS_IN_USART_FRAME) && (BITBANG_TPIDATA_PIN & BITBANG_TPIDATA_MASK))
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return;
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/* Shift in the bit one less than the frame size in position, so that the start bit will eventually
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* be discarded leaving the data to be byte-aligned for quick access (subtract 9 as we are ORing to the MSB) */
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if (BITBANG_TPIDATA_PIN & BITBANG_TPIDATA_MASK)
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((uint8_t*)&SoftUSART_Data)[1] |= (1 << (BITS_IN_USART_FRAME - 9));
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SoftUSART_Data >>= 1;
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SoftUSART_BitCount--;
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}
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else
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{
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/* If at falling clock edge and we are in receive mode, abort */
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if (!IsSending)
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return;
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/* Set the data line to the next bit value */
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if (((uint8_t*)&SoftUSART_Data)[0] & 0x01)
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BITBANG_TPIDATA_PORT |= BITBANG_TPIDATA_MASK;
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else
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BITBANG_TPIDATA_PORT &= ~BITBANG_TPIDATA_MASK;
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SoftUSART_Data >>= 1;
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SoftUSART_BitCount--;
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}
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}
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#endif
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volatile bool IsSending;
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/** Enables the target's PDI interface, holding the target in reset until PDI mode is exited. */
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void XPROGTarget_EnableTargetPDI(void)
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{
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IsSending = false;
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#if defined(XPROG_VIA_HARDWARE_USART)
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/* Set Tx and XCK as outputs, Rx as input */
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DDRD |= (1 << 5) | (1 << 3);
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DDRD &= ~(1 << 2);
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@ -160,24 +58,6 @@ void XPROGTarget_EnableTargetPDI(void)
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UBRR1 = (F_CPU / XPROG_HARDWARE_SPEED);
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UCSR1B = (1 << TXEN1);
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UCSR1C = (1 << UMSEL10) | (1 << UPM11) | (1 << USBS1) | (1 << UCSZ11) | (1 << UCSZ10) | (1 << UCPOL1);
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#else
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/* Set DATA and CLOCK lines to outputs */
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BITBANG_PDIDATA_DDR |= BITBANG_PDIDATA_MASK;
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BITBANG_PDICLOCK_DDR |= BITBANG_PDICLOCK_MASK;
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/* Set DATA line low for at least 1ms to ensure that the device is ready for PDI mode to be entered */
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BITBANG_PDIDATA_PORT &= ~BITBANG_PDIDATA_MASK;
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_delay_ms(1);
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/* Set DATA line high for at least 90ns to disable /RESET functionality */
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BITBANG_PDIDATA_PORT |= BITBANG_PDIDATA_MASK;
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_delay_us(1);
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/* Fire timer compare channel A ISR to manage the software USART */
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OCR1A = BITS_BETWEEN_USART_CLOCKS;
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TCCR1B = (1 << WGM12) | (1 << CS10);
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TIMSK1 = (1 << OCIE1A);
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#endif
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/* Send two BREAKs of 12 bits each to enable PDI interface (need at least 16 idle bits) */
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XPROGTarget_SendBreak();
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@ -194,7 +74,6 @@ void XPROGTarget_EnableTargetTPI(void)
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AUX_LINE_PORT &= ~AUX_LINE_MASK;
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_delay_us(1);
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#if defined(XPROG_VIA_HARDWARE_USART)
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/* Set Tx and XCK as outputs, Rx as input */
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DDRD |= (1 << 5) | (1 << 3);
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DDRD &= ~(1 << 2);
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@ -203,19 +82,6 @@ void XPROGTarget_EnableTargetTPI(void)
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UBRR1 = (F_CPU / XPROG_HARDWARE_SPEED);
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UCSR1B = (1 << TXEN1);
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UCSR1C = (1 << UMSEL10) | (1 << UPM11) | (1 << USBS1) | (1 << UCSZ11) | (1 << UCSZ10) | (1 << UCPOL1);
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#else
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/* Set DATA and CLOCK lines to outputs */
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BITBANG_TPIDATA_DDR |= BITBANG_TPIDATA_MASK;
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BITBANG_TPICLOCK_DDR |= BITBANG_TPICLOCK_MASK;
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/* Set DATA line high for idle state */
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BITBANG_TPIDATA_PORT |= BITBANG_TPIDATA_MASK;
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/* Fire timer capture channel ISR to manage the software USART */
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ICR1 = BITS_BETWEEN_USART_CLOCKS;
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TCCR1B = (1 << WGM13) | (1 << WGM12) | (1 << CS10);
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TIMSK1 = (1 << ICIE1);
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#endif
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/* Send two BREAKs of 12 bits each to enable TPI interface (need at least 16 idle bits) */
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XPROGTarget_SendBreak();
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@ -228,7 +94,6 @@ void XPROGTarget_DisableTargetPDI(void)
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/* Switch to Rx mode to ensure that all pending transmissions are complete */
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XPROGTarget_SetRxMode();
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#if defined(XPROG_VIA_HARDWARE_USART)
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/* Turn off receiver and transmitter of the USART, clear settings */
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UCSR1A = ((1 << TXC1) | (1 << RXC1));
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UCSR1B = 0;
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@ -237,18 +102,6 @@ void XPROGTarget_DisableTargetPDI(void)
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/* Tristate all pins */
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DDRD &= ~((1 << 5) | (1 << 3));
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PORTD &= ~((1 << 5) | (1 << 3) | (1 << 2));
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#else
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/* Turn off software USART management timer */
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TCCR1B = 0;
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/* Set DATA and CLOCK lines to inputs */
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BITBANG_PDIDATA_DDR &= ~BITBANG_PDIDATA_MASK;
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BITBANG_PDICLOCK_DDR &= ~BITBANG_PDICLOCK_MASK;
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/* Tristate DATA and CLOCK lines */
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BITBANG_PDIDATA_PORT &= ~BITBANG_PDIDATA_MASK;
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BITBANG_PDICLOCK_PORT &= ~BITBANG_PDICLOCK_MASK;
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#endif
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}
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/** Disables the target's TPI interface, exits programming mode and starts the target's application. */
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@ -257,7 +110,6 @@ void XPROGTarget_DisableTargetTPI(void)
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/* Switch to Rx mode to ensure that all pending transmissions are complete */
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XPROGTarget_SetRxMode();
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#if defined(XPROG_VIA_HARDWARE_USART)
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/* Turn off receiver and transmitter of the USART, clear settings */
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UCSR1A |= (1 << TXC1) | (1 << RXC1);
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UCSR1B = 0;
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@ -266,18 +118,6 @@ void XPROGTarget_DisableTargetTPI(void)
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/* Set all USART lines as input, tristate */
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DDRD &= ~((1 << 5) | (1 << 3));
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PORTD &= ~((1 << 5) | (1 << 3) | (1 << 2));
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#else
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/* Turn off software USART management timer */
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TCCR1B = 0;
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/* Set DATA and CLOCK lines to inputs */
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BITBANG_TPIDATA_DDR &= ~BITBANG_TPIDATA_MASK;
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BITBANG_TPICLOCK_DDR &= ~BITBANG_TPICLOCK_MASK;
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/* Tristate DATA and CLOCK lines */
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BITBANG_TPIDATA_PORT &= ~BITBANG_TPIDATA_MASK;
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BITBANG_TPICLOCK_PORT &= ~BITBANG_TPICLOCK_MASK;
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#endif
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/* Tristate target /RESET line */
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AUX_LINE_DDR &= ~AUX_LINE_MASK;
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@ -294,30 +134,10 @@ void XPROGTarget_SendByte(const uint8_t Byte)
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if (!(IsSending))
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XPROGTarget_SetTxMode();
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#if defined(XPROG_VIA_HARDWARE_USART)
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/* Wait until there is space in the hardware Tx buffer before writing */
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while (!(UCSR1A & (1 << UDRE1)));
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UCSR1A |= (1 << TXC1);
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UDR1 = Byte;
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#else
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/* Calculate the new USART frame data here while while we wait for a previous byte (if any) to finish sending */
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uint16_t NewUSARTData = ((1 << 11) | (1 << 10) | (0 << 9) | ((uint16_t)Byte << 1) | (0 << 0));
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/* Compute Even parity - while a bit is still set, chop off lowest bit and toggle parity bit */
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uint8_t ParityData = Byte;
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while (ParityData)
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{
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NewUSARTData ^= (1 << 9);
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ParityData &= (ParityData - 1);
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}
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/* Wait until transmitter is idle before writing new data */
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while (SoftUSART_BitCount);
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/* Data shifted out LSB first, START DATA PARITY STOP STOP */
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SoftUSART_Data = NewUSARTData;
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SoftUSART_BitCount = BITS_IN_USART_FRAME;
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#endif
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if (TimeoutMSRemaining)
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TimeoutMSRemaining = COMMAND_TIMEOUT_MS;
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@ -333,7 +153,6 @@ uint8_t XPROGTarget_ReceiveByte(void)
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if (IsSending)
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XPROGTarget_SetRxMode();
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#if defined(XPROG_VIA_HARDWARE_USART)
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/* Wait until a byte has been received before reading */
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while (!(UCSR1A & (1 << RXC1)) && TimeoutMSRemaining);
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||||
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@ -341,17 +160,6 @@ uint8_t XPROGTarget_ReceiveByte(void)
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TimeoutMSRemaining = COMMAND_TIMEOUT_MS;
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||||
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||||
return UDR1;
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||||
#else
|
||||
/* Wait until a byte has been received before reading */
|
||||
SoftUSART_BitCount = BITS_IN_USART_FRAME;
|
||||
while (SoftUSART_BitCount && TimeoutMSRemaining);
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||||
|
||||
if (TimeoutMSRemaining)
|
||||
TimeoutMSRemaining = COMMAND_TIMEOUT_MS;
|
||||
|
||||
/* Throw away the parity and stop bits to leave only the data (start bit is already discarded) */
|
||||
return (uint8_t)SoftUSART_Data;
|
||||
#endif
|
||||
}
|
||||
|
||||
/** Sends a BREAK via the USART to the attached target, consisting of a full frame of idle bits. */
|
||||
|
|
@ -361,7 +169,6 @@ void XPROGTarget_SendBreak(void)
|
|||
if (!(IsSending))
|
||||
XPROGTarget_SetTxMode();
|
||||
|
||||
#if defined(XPROG_VIA_HARDWARE_USART)
|
||||
/* Need to do nothing for a full frame to send a BREAK */
|
||||
for (uint8_t i = 0; i < BITS_IN_USART_FRAME; i++)
|
||||
{
|
||||
|
|
@ -369,13 +176,6 @@ void XPROGTarget_SendBreak(void)
|
|||
while (PIND & (1 << 5));
|
||||
while (!(PIND & (1 << 5)));
|
||||
}
|
||||
#else
|
||||
while (SoftUSART_BitCount);
|
||||
|
||||
/* Need to do nothing for a full frame to send a BREAK */
|
||||
SoftUSART_Data = 0x0FFF;
|
||||
SoftUSART_BitCount = BITS_IN_USART_FRAME;
|
||||
#endif
|
||||
|
||||
if (TimeoutMSRemaining)
|
||||
TimeoutMSRemaining = COMMAND_TIMEOUT_MS;
|
||||
|
|
@ -383,7 +183,6 @@ void XPROGTarget_SendBreak(void)
|
|||
|
||||
static void XPROGTarget_SetTxMode(void)
|
||||
{
|
||||
#if defined(XPROG_VIA_HARDWARE_USART)
|
||||
/* Wait for a full cycle of the clock */
|
||||
while (PIND & (1 << 5));
|
||||
while (!(PIND & (1 << 5)));
|
||||
|
|
@ -395,25 +194,6 @@ static void XPROGTarget_SetTxMode(void)
|
|||
UCSR1B |= (1 << TXEN1);
|
||||
|
||||
IsSending = true;
|
||||
#else
|
||||
while (SoftUSART_BitCount && TimeoutMSRemaining);
|
||||
|
||||
/* Wait for a full cycle of the clock */
|
||||
SoftUSART_Data = 0x0001;
|
||||
SoftUSART_BitCount = 1;
|
||||
while (SoftUSART_BitCount);
|
||||
|
||||
if (XPROG_SelectedProtocol == XPRG_PROTOCOL_PDI)
|
||||
{
|
||||
BITBANG_PDIDATA_PORT |= BITBANG_PDIDATA_MASK;
|
||||
BITBANG_PDIDATA_DDR |= BITBANG_PDIDATA_MASK;
|
||||
}
|
||||
else
|
||||
{
|
||||
BITBANG_TPIDATA_PORT |= BITBANG_TPIDATA_MASK;
|
||||
BITBANG_TPIDATA_DDR |= BITBANG_TPIDATA_MASK;
|
||||
}
|
||||
#endif
|
||||
|
||||
if (TimeoutMSRemaining)
|
||||
TimeoutMSRemaining = COMMAND_TIMEOUT_MS;
|
||||
|
|
@ -423,7 +203,6 @@ static void XPROGTarget_SetTxMode(void)
|
|||
|
||||
static void XPROGTarget_SetRxMode(void)
|
||||
{
|
||||
#if defined(XPROG_VIA_HARDWARE_USART)
|
||||
while (!(UCSR1A & (1 << TXC1)));
|
||||
UCSR1A |= (1 << TXC1);
|
||||
|
||||
|
|
@ -432,26 +211,6 @@ static void XPROGTarget_SetRxMode(void)
|
|||
|
||||
DDRD &= ~(1 << 3);
|
||||
PORTD &= ~(1 << 3);
|
||||
#else
|
||||
while (SoftUSART_BitCount && TimeoutMSRemaining);
|
||||
|
||||
if (XPROG_SelectedProtocol == XPRG_PROTOCOL_PDI)
|
||||
{
|
||||
BITBANG_PDIDATA_DDR &= ~BITBANG_PDIDATA_MASK;
|
||||
BITBANG_PDIDATA_PORT &= ~BITBANG_PDIDATA_MASK;
|
||||
|
||||
/* Wait until DATA line has been pulled up to idle by the target */
|
||||
while (!(BITBANG_PDIDATA_PIN & BITBANG_PDIDATA_MASK) && TimeoutMSRemaining);
|
||||
}
|
||||
else
|
||||
{
|
||||
BITBANG_TPIDATA_DDR &= ~BITBANG_TPIDATA_MASK;
|
||||
BITBANG_TPIDATA_PORT &= ~BITBANG_TPIDATA_MASK;
|
||||
|
||||
/* Wait until DATA line has been pulled up to idle by the target */
|
||||
while (!(BITBANG_TPIDATA_PIN & BITBANG_TPIDATA_MASK) && TimeoutMSRemaining);
|
||||
}
|
||||
#endif
|
||||
|
||||
if (TimeoutMSRemaining)
|
||||
TimeoutMSRemaining = COMMAND_TIMEOUT_MS;
|
||||
|
|
|
|||
|
|
@ -54,38 +54,10 @@
|
|||
#define ENABLE_XPROG_PROTOCOL
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* Defines: */
|
||||
#if ((BOARD == BOARD_XPLAIN) || (BOARD == BOARD_XPLAIN_REV1))
|
||||
#define XPROG_VIA_HARDWARE_USART
|
||||
#else
|
||||
#define BITBANG_PDIDATA_PORT PORTB
|
||||
#define BITBANG_PDIDATA_DDR DDRB
|
||||
#define BITBANG_PDIDATA_PIN PINB
|
||||
#define BITBANG_PDIDATA_MASK (1 << 3)
|
||||
|
||||
#define BITBANG_PDICLOCK_PORT AUX_LINE_PORT
|
||||
#define BITBANG_PDICLOCK_DDR AUX_LINE_DDR
|
||||
#define BITBANG_PDICLOCK_PIN AUX_LINE_PIN
|
||||
#define BITBANG_PDICLOCK_MASK AUX_LINE_MASK
|
||||
|
||||
#define BITBANG_TPIDATA_PORT PORTB
|
||||
#define BITBANG_TPIDATA_DDR DDRB
|
||||
#define BITBANG_TPIDATA_PIN PINB
|
||||
#define BITBANG_TPIDATA_MASK (1 << 3)
|
||||
|
||||
#define BITBANG_TPICLOCK_PORT PORTB
|
||||
#define BITBANG_TPICLOCK_DDR DDRB
|
||||
#define BITBANG_TPICLOCK_PIN PINB
|
||||
#define BITBANG_TPICLOCK_MASK (1 << 1)
|
||||
#endif
|
||||
|
||||
/** Serial carrier TPI/PDI speed when hardware TPI/PDI mode is used */
|
||||
#define XPROG_HARDWARE_SPEED 1000000
|
||||
|
||||
/** Number of cycles between each clock when software USART mode is used */
|
||||
#define BITS_BETWEEN_USART_CLOCKS 100
|
||||
|
||||
/** Total number of bits in a single USART frame */
|
||||
#define BITS_IN_USART_FRAME 12
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue