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When automatic PLL management mode is enabled on the U4 series AVR8 chips, the PLL is now configured for 48MHz and not a divided 96MHz, to lower power consumption and to keep the system within the datasheet specs for 3.3V operation (thanks to Scott Vitale).

This commit is contained in:
Dean Camera 2011-10-12 02:27:22 +00:00
parent 1a4a26271e
commit c15eaa5dae
2 changed files with 3 additions and 2 deletions
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2
LUFA/Drivers/USB/Core/AVR8/USBController_AVR8.c
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@ -68,7 +68,7 @@ void USB_Init(
if (!(USB_Options & USB_OPT_MANUAL_PLL)) if (!(USB_Options & USB_OPT_MANUAL_PLL))
{ {
#if defined(USB_SERIES_4_AVR) #if defined(USB_SERIES_4_AVR)
PLLFRQ = ((1 << PLLUSB) | (1 << PDIV3) | (1 << PDIV1)); PLLFRQ = (1 << PDIV2);
#endif #endif
} }

3
LUFA/ManPages/ChangeLog.txt
View File

@ -15,7 +15,8 @@
* *
* <b>Changed:</b> * <b>Changed:</b>
* - Core: * - Core:
* - None * - When automatic PLL management mode is enabled on the U4 series AVR8 chips, the PLL is now configured for 48MHz and not
* a divided 96MHz, to lower power consumption and to keep the system within the datasheet specs for 3.3V operation (thanks to Scott Vitale)
* - Library Applications: * - Library Applications:
* - None * - None
* *