forked from mfulz_github/qmk_firmware
Update Doxygen configuration files to the latest Doxygen version.
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@ -10,6 +10,7 @@
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*
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* The following list indicates what microcontrollers are compatible with this demo.
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*
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* - AT90USB162 (Teensy 1.0)
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* - ATMEGA32U4 (Teensy 2.0)
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*
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* \section SSec_Info USB Information:
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1343
LUFA/Doxygen.conf
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@ -19,7 +19,7 @@
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* - Added new MIDI send buffer flush routines to the MIDI Device and Host mode Class drivers, to flush packed events
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*
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* <b>Changed:</b>
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* - Slowed down bit-banged PDI programming in the AVRISP project slightly to prevent transmission errors
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* - Slowed down PDI programming in the AVRISP project to prevent transmission errors
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* - Renamed the AVRISP project folder to AVRISP-MKII to reduce confusion
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* - Renamed the RESET_LINE_* makefile tokens in the AVRISP MKII Project to AUX_LINE_*, as they are not always used for target
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* reset
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@ -53,7 +53,7 @@
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* This device spoofs Atmel's official AVRISP-MKII device PID so that it remains compatible with Atmel's AVRISP-MKII
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* drivers. When prompted, direct your OS to install Atmel's AVRISP-MKII drivers provided with AVRStudio.
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*
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* Note that this design currently has several limitations:
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* Note that this design currently has the following limitations:
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* - Minimum ISP target clock speed of 500KHz due to hardware SPI module prescaler limitations
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* - No reversed/shorted target connector detection and notification
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*
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@ -62,7 +62,9 @@
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* without an ADC converter, VTARGET will report a fixed 5V level at all times.
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*
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* When compiled for the XPLAIN board target, this will automatically configure itself for the correct connections to the
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* XPLAIN's XMEGA AVR, and will enable PDI/TPI only programming support (since ISP mode is not needed).
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* XPLAIN's XMEGA AVR, and will enable PDI/TPI only programming support (since ISP mode is not needed). Note that the
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* first revision XPLAIN board lacks a bootloader on the AT90USB1287, and thus for this firmware to be loaded, an external
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* programmer will be required.
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*
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* While this application can be compiled for USB AVRs with as little as 8KB of FLASH, for full functionality 16KB or more
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* of FLASH is required. On 8KB devices, ISP or PDI/TPI programming support can be disabled to reduce program size.
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@ -53,14 +53,14 @@ uint8_t ISPTarget_GetSPIPrescalerMask(void)
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SPI_SPEED_FCPU_DIV_8, // AVRStudio = 1MHz SPI, Actual = 1MHz SPI
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SPI_SPEED_FCPU_DIV_16, // AVRStudio = 500KHz SPI, Actual = 500KHz SPI
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SPI_SPEED_FCPU_DIV_32, // AVRStudio = 250KHz SPI, Actual = 250KHz SPI
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SPI_SPEED_FCPU_DIV_64 // AVRStudio = 125KHz SPI, Actual = 125KHz SPI
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SPI_SPEED_FCPU_DIV_64, // AVRStudio = 125KHz SPI, Actual = 125KHz SPI
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#elif (F_CPU == 16000000)
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SPI_SPEED_FCPU_DIV_2, // AVRStudio = 8MHz SPI, Actual = 8MHz SPI
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SPI_SPEED_FCPU_DIV_4, // AVRStudio = 4MHz SPI, Actual = 4MHz SPI
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SPI_SPEED_FCPU_DIV_8, // AVRStudio = 2MHz SPI, Actual = 2MHz SPI
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SPI_SPEED_FCPU_DIV_16, // AVRStudio = 1MHz SPI, Actual = 1MHz SPI
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SPI_SPEED_FCPU_DIV_32, // AVRStudio = 500KHz SPI, Actual = 500KHz SPI
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SPI_SPEED_FCPU_DIV_64, // AVRStudio = 250KHz SPI, Actual = 250KHz SPI
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SPI_SPEED_FCPU_DIV_64, // AVRStudio = 250KHz SPI, Actual = 250KHz SPI
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SPI_SPEED_FCPU_DIV_128 // AVRStudio = 125KHz SPI, Actual = 125KHz SPI
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#else
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#error No SPI prescaler masks for chosen F_CPU speed.
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@ -171,7 +171,7 @@ uint8_t ISPTarget_WaitWhileTargetBusy(void)
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*/
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void ISPTarget_LoadExtendedAddress(void)
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{
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SPI_SendByte(0x4D);
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SPI_SendByte(LOAD_EXTENDED_ADDRESS_CMD);
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SPI_SendByte(0x00);
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SPI_SendByte((CurrentAddress & 0x00FF0000) >> 16);
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SPI_SendByte(0x00);
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@ -58,6 +58,8 @@
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/** Total number of allowable ISP programming speeds supported by the device */
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#define TOTAL_ISP_PROGRAMMING_SPEEDS 7
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#define LOAD_EXTENDED_ADDRESS_CMD 0x4D
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/* Function Prototypes: */
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uint8_t ISPTarget_GetSPIPrescalerMask(void);
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void ISPTarget_ChangeTargetResetLine(const bool ResetTarget);
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@ -159,7 +159,7 @@ void XPROGTarget_EnableTargetPDI(void)
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/* Set up the synchronous USART for XMEGA communications -
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8 data bits, even parity, 2 stop bits */
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UBRR1 = (F_CPU / 1000000UL);
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UBRR1 = (F_CPU / 500000UL);
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UCSR1B = (1 << TXEN1);
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UCSR1C = (1 << UMSEL10) | (1 << UPM11) | (1 << USBS1) | (1 << UCSZ11) | (1 << UCSZ10) | (1 << UCPOL1);
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#else
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@ -201,7 +201,7 @@ void XPROGTarget_EnableTargetTPI(void)
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/* Set up the synchronous USART for XMEGA communications -
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8 data bits, even parity, 2 stop bits */
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UBRR1 = (F_CPU / 1000000UL);
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UBRR1 = (F_CPU / 500000UL);
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UCSR1B = (1 << TXEN1);
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UCSR1C = (1 << UMSEL10) | (1 << UPM11) | (1 << USBS1) | (1 << UCSZ11) | (1 << UCSZ10) | (1 << UCPOL1);
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#else
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