forked from mfulz_github/qmk_firmware
Updated John Steggall's software USART in the XPLAINBridge project.
This commit is contained in:
parent
ab602a8b48
commit
f37d21bbe9
File diff suppressed because one or more lines are too long
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@ -31,6 +31,7 @@
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* -# Keyboard/Mouse Dual Class Host
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* -# Keyboard/Mouse Dual Class Host
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* -# Multiple-Report HID device
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* -# Multiple-Report HID device
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* -# Device/Host bridge
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* -# Device/Host bridge
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* -# PDI Programming Support in the AVRISP Project
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* - Ports
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* - Ports
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* -# AVR32 UC3B series microcontrollers
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* -# AVR32 UC3B series microcontrollers
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* -# Atmel ARM7 series microcontrollers
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* -# Atmel ARM7 series microcontrollers
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@ -2,6 +2,8 @@
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uart_soft
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uart_soft
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v0.2
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copyright John Steggall 2009
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copyright John Steggall 2009
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*/
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*/
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@ -30,10 +32,8 @@
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*/
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*/
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#include <avr/io.h>
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#include <avr/io.h>
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#include "SoftUARTConf.h"
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/* BITLENGTH is the time for a bit cycle worked out at F_CPU / BAUD. Gives a rough but usable figure. Wouldn't like to try
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* anything faster than 9600! */
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#define BITLENGTH 833
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#define SFT_TX_EN 7
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#define SFT_TX_EN 7
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@ -52,43 +52,59 @@ rxShifter:
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.byte 0
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.byte 0
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rxBitcount:
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rxBitcount:
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.byte 0
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.byte 0
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.global status
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status:
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status:
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.byte 0
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.byte 0
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.section .text
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.section .text
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.global RX_PIN_INT
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/*********************************************
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/*********************************************
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* External interrupt
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* External interrupt
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*
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*
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* RX pin has gone low.
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* RX pin has gone low.
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*/
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*/
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.global INT0_vect
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RX_PIN_INT:
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INT0_vect:
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push r16
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push r16
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lds r16,SREG
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lds r16,SREG
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push r16
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push r16
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lds r16,PIND
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#if (RXPORT>=32)
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lds r16,RXPORT
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sbrc r16,0 // anti glitch
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sbrc r16,0 // anti glitch
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#else
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sbic RXPORT,0
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#endif
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rjmp ignore
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rjmp ignore
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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lds r16,PIND
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sbrc r16,0 // just make sure
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#if (RXPORT>=32)
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lds r16,RXPORT
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sbrc r16,0 // anti glitch
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#else
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sbic RXPORT,0
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#endif
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rjmp ignore
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rjmp ignore
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push r17
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push r17
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// grab timer value
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// grab timer value
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lds r16,TCNT3L
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lds r16,TC_COUNTL
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lds r17,TCNT3H
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lds r17,TC_COUNTH
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// set trigger for RX timer (will need to add a little more though)
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// set trigger for RX timer (will need to add a little more though)
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sts OCR3CH,r17
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sts TC_RX_COMPH,r17
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sts OCR3CL,r16
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sts TC_RX_COMPL,r16
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pop r17
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pop r17
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@ -98,13 +114,15 @@ INT0_vect:
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// turn off interrupt, will get annoying.
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// turn off interrupt, will get annoying.
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cbi 0x1D,0
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cbi EXTI_MASK_REG,EXTI_MASK_BIT
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// turn on interrupt on compare match
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// turn on interrupt on compare match
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sbi 0x18,OCF3C
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lds r16,TIMSK3
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sbi TC_INTFLAG_REG,TC_RX_IF_BIT //------------------------
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ori r16,(1<<OCIE3C)
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sts TIMSK3,r16
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lds r16,TC_INT_MASK_REG
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ori r16,(1<<TC_RX_COMPEN)
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sts TC_INT_MASK_REG,r16
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ignore:
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ignore:
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pop r16
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pop r16
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@ -136,17 +154,23 @@ TIMER3_COMPB_vect:
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lds r16,txShifter
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lds r16,txShifter
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lds r17, PORTD
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#if (TXPORT>=32)
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lds r17, TXPORT
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sbrs r16,0
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sbrs r16,0
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andi r17,0xFD
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andi r17,~(1<<TXPIN)
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sbrc r16,0
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sbrc r16,0
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ori r17,0x02
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ori r17,(1<<TXPIN)
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sts TXPORT,r17
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sts PORTD,r17
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#else
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sbrs r16,0
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cbi TXPORT,TXPIN
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sbrc r16,0
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sbi TXPORT,TXPIN
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lsr r16
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#endif
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ori r16,0x80
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sec
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ror r16
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txout:
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txout:
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sts txShifter,r16
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sts txShifter,r16
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ori r17,SF_UART_TX // set TXC/DRE flag
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ori r17,SF_UART_TX // set TXC/DRE flag
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sts status,r17
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sts status,r17
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lds r16,TIMSK3
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lds r16,TC_INT_MASK_REG
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andi r16,~(1<<OCIE3B)
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andi r16,~(1<<TC_TX_COMPEN)
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sts TIMSK3,r16
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sts TC_INT_MASK_REG,r16
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rjmp lastBitOut // over and out
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rjmp lastBitOut // over and out
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@ -199,11 +223,27 @@ TIMER3_COMPC_vect:
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ldi r18,3 // set counter to 3
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ldi r18,3 // set counter to 3
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ldi r17,0
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ldi r17,0
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// cbi 0x0B,1 // marker
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#ifdef DEBUG
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#if RXPORT>64
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lds r16,RXPORT
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andi r16,~(1<<TXPIN)
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sts TXPORT,r16
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#else
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cbi TXPORT,TXPIN // marker
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#endif
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#endif
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loopGetBit:
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loopGetBit:
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lds r16,PIND
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sbrc r16,0
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#if (RXPORT>=32)
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lds r16,RXPORT
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sbrs r16,RXPIN
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#else
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sbic RXPORT,RXPIN
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#endif
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inc r17
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inc r17
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dec r18
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dec r18
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nop
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nop
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@ -212,7 +252,19 @@ loopGetBit:
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nop
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nop
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brne loopGetBit
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brne loopGetBit
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// sbi 0x0B,1 // marker
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#ifdef DEBUG
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#if RXPORT>64
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lds r16,RXPORT
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ori r16,1<<TXPIN
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sts r16
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#else
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sbi TXPORT,TXPIN // marker
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#endif
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#endif
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lds r16,rxShifter
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lds r16,rxShifter
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lsr r16
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lsr r16
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@ -226,8 +278,16 @@ skipBitSet:
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lastBitRX:
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lastBitRX:
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lds r17,status // store status
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lds r17,status // store status
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lds r16,PIND // get status of stop bit
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sbrc r16,0
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#if (RXPORT>=32)
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lds r16,RXPORT
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sbrc r16,RXPIN
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#else
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sbic RXPORT,RXPIN
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#endif
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ori r17,0x02 // set flag if stop bit was high
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ori r17,0x02 // set flag if stop bit was high
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sts status,r17
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sts status,r17
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// switch interrupt back on to get another go
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// switch interrupt back on to get another go
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sbi 0x1C,0 // clear interrupt flag
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sbi EXTI_FLAG_REG,EXTI_MASK_BIT // clear interrupt flag
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sbi 0x1D,0 // enable external interrupt 0 (RX)
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sbi EXTI_MASK_REG,EXTI_MASK_BIT // enable external interrupt 0 (RX)
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// switch off rx bit timer
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// switch off rx bit timer
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lds r16,TIMSK3
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lds r16,TC_INT_MASK_REG
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andi r16,~(1<<OCIE3C)
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andi r16,~(1<<TC_RX_COMPEN)
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sts TIMSK3,r16
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sts TC_INT_MASK_REG,r16
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rjmp lastBitOut // loud and clear
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rjmp lastBitOut // loud and clear
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rx1stbit:
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rx1stbit:
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lds r16,TCNT3L
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lds r16,TC_COUNTL
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lds r17,TCNT3H
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lds r17,TC_COUNTH
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subi r16,lo8(BITLENGTH / 2)
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subi r16,lo8(BITLENGTH / 2)
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sbci r17,hi8(BITLENGTH / 2)
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sbci r17,hi8(BITLENGTH / 2)
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@ -259,8 +319,8 @@ rx1stbit:
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sbci r17,hi8(0xFFFF - BITLENGTH)
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sbci r17,hi8(0xFFFF - BITLENGTH)
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skipOverflow:
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skipOverflow:
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sts OCR3CH,r17
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sts TC_RX_COMPH,r17
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sts OCR3CL,r17
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sts TC_RX_COMPL,r17
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rjmp lastBitOut
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rjmp lastBitOut
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SoftUART_Init:
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SoftUART_Init:
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lds r18,PORTD
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#if (TXPORT>=32)
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lds r18,TXPORT
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ori r18,0x02
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ori r18,0x02
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sts PORTD,r18
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sts TXPORT,r18
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lds r18,DDRD
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lds r18,TXDIR_REG
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ori r18,0x02
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ori r18,0x02
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sts DDRD,r18
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sts TXDIR_REG,r18
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#else
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sbi TXPORT,TXPIN
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sbi TXDIR_REG,TXPIN
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#endif
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ldi r18,(1<<SFT_TX_EN)|SF_UART_TX
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ldi r18,(1<<SFT_TX_EN)|SF_UART_TX
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sts status,r18
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sts status,r18
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@ -290,17 +358,17 @@ SoftUART_Init:
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// Start timer 3
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// Start timer 3
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ldi r18,0b00001001 // ctc count mode, clock div 1
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ldi r18,0b00001001 // ctc count mode, clock div 1
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sts TCCR3B,r18
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sts TC_CTRLB,r18
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// Interrupt on low level INT0
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// Interrupt on pin change INT0
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sbi 0x1C,0
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sbi EXTI_FLAG_REG,EXTI_MASK_BIT
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sbi 0x1D,0
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sbi EXTI_MASK_REG,EXTI_MASK_BIT
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ret
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ret
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/*********************************************
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/*********************************************
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* char SoftUART_TxByte(char)
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* char SoftUART_RxByte(char)
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*
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*
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* starts a byte send and returns the byte to be sent
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* starts a byte send and returns the byte to be sent
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*/
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*/
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SoftUART_TxByte:
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SoftUART_TxByte:
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lds r18,status
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lds r18,status
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sbrs r18,SFT_TX_EN
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sbrs r18,SFT_TX_EN
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rjmp uart_putchar_end
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rjmp SoftUART_TxByte_end
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andi r18,0xFE // clear tx empty flag
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andi r18,0xFE // clear tx empty flag
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sts status,r18
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sts status,r18
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@ -320,28 +388,35 @@ SoftUART_TxByte:
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sts txBitcount,r18
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sts txBitcount,r18
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// grab timer value
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// grab timer value
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cli // Atomic section start
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lds r18,TCNT3L
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lds r18,TC_COUNTL
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lds r19,TCNT3H
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lds r19,TC_COUNTH
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// drop down tx line for start bit
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// drop down tx line for start bit
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lds r20, PORTD
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andi r20,0xFD
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#if (TXPORT>=32)
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sts PORTD,r20
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lds r20, TXPORT
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andi r20,~(1<<TXPIN)
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sts TXPORT,r20
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#else
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cbi TXPORT,TXPIN
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#endif
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// set trigger for tx timer
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// set trigger for tx timer
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cli
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sts TC_TX_COMPH,r19
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sts OCR3BH,r19
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sts TC_TX_COMPL,r18
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sts OCR3BL,r18
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sei // Atomic section end
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sei
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// clear interrupt flag and enable tx interrupt
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// clear interrupt flag and enable tx interrupt
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sbi 0x18,OCF3B
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lds r18,TIMSK3
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ori r18,(1<<OCIE3B)
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sts TIMSK3,r18
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uart_putchar_end:
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sbi TC_INTFLAG_REG,TC_TX_IF_BIT
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lds r18,TC_INT_MASK_REG
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ori r18,(1<<TC_TX_COMPEN)
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sts TC_INT_MASK_REG,r18
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SoftUART_TxByte_end:
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ret
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ret
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@ -2,6 +2,8 @@
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soft_uart
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soft_uart
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v0.2
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Copyright John Steggall 2009
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Copyright John Steggall 2009
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*/
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*/
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*/
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*/
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/*
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/*
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Specifically designed for the xplain board, other uses could be made by furkling through the code
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Specifically designed for the xplain board, other uses could be made by adjusting uart_soft_conf.h
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and replacing the port and pin assignments. Also relies on and external interupt to detect the low
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replacing the port, pin and timer assignments. Also relies on and external interupt to detect the low
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level of the start bit, in this case INT0.
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level of the start bit, in this case INT0.
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Always configured to 9600baud. Can be changed by setting the BITLENGTH define to F_CPU/(desired baud)
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Always configured to 9600baud. Can be changed by setting the BITLENGTH define to F_CPU/(desired baud)
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code may need optimising when getting any faster to sample the bit in the correct place. No
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code may need optimising when getting any faster to sample the bit in the correct place. No
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compensation has been made for the response time of the int routine.
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compensation has been made for the response time of the int routine.
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Note: Configured to use 16bit timers.
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*/
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/* Changes
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*
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* v0.2
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* - Added configuration file to ease pain of setup for different hardware configuration
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* - Changed bit access for ports that can be accessed directly
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* - Fixed atomic section in uart_init to encompass counter read
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*/
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*/
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#ifndef UART_SOFT_H
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#ifndef UART_SOFT_H
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#define UART_SOFT_H
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#define UART_SOFT_H
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/* status */
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extern uint8_t status;
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/* initialises software uart and enables transmit */
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/* initialises software uart and enables transmit */
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extern void SoftUART_Init(void);
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extern void SoftUART_Init(void);
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||||||
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@ -0,0 +1,75 @@
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/*
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||||||
|
|
||||||
|
soft_uart
|
||||||
|
|
||||||
|
v0.2
|
||||||
|
|
||||||
|
Copyright John Steggall 2009
|
||||||
|
|
||||||
|
*/
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||||||
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||||||
|
/*
|
||||||
|
Copyright 2009 John Steggall (steggall.j@gmail.com)
|
||||||
|
|
||||||
|
Permission to use, copy, modify, and distribute this software
|
||||||
|
and its documentation for any purpose and without fee is hereby
|
||||||
|
granted, provided that the above copyright notice appear in all
|
||||||
|
copies and that both that the copyright notice and this
|
||||||
|
permission notice and warranty disclaimer appear in supporting
|
||||||
|
documentation, and that the name of the author not be used in
|
||||||
|
advertising or publicity pertaining to distribution of the
|
||||||
|
software without specific, written prior permission.
|
||||||
|
|
||||||
|
The author disclaim all warranties with regard to this
|
||||||
|
software, including all implied warranties of merchantability
|
||||||
|
and fitness. In no event shall the author be liable for any
|
||||||
|
special, indirect or consequential damages or any damages
|
||||||
|
whatsoever resulting from loss of use, data or profits, whether
|
||||||
|
in an action of contract, negligence or other tortious action,
|
||||||
|
arising out of or in connection with the use or performance of
|
||||||
|
this software.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef UART_SOFT_CONF
|
||||||
|
#define UART_SOFT_CONF
|
||||||
|
|
||||||
|
#define BITLENGTH 833 // Length of data bit, worked out by F_CPU/desired baud
|
||||||
|
|
||||||
|
#define TXPIN 1 // Port pin TX is connected to
|
||||||
|
#define RXPIN 0 // Port pin RX is connected to
|
||||||
|
|
||||||
|
/* PORT setup */
|
||||||
|
#define RXPORT 0x09 // RX port selection
|
||||||
|
#define TXPORT 0x0B // TX port selection
|
||||||
|
#define TXDIR_REG 0x0A // Data direction port for TX pin
|
||||||
|
|
||||||
|
/* RX pin setup */
|
||||||
|
#define EXTI_FLAG_REG 0x1C
|
||||||
|
#define EXTI_MASK_REG 0x1D
|
||||||
|
#define EXTI_MASK_BIT 0
|
||||||
|
|
||||||
|
#define RX_PIN_INT INT0_vect // external interrupt vector for RX pin
|
||||||
|
#define RX_INT_vect TIMER3_COMPC_vect // interrupt vector for OCRnC
|
||||||
|
#define TX_INT_vect TIMER3_COMPB_vect // interrupt vector for OCRnB
|
||||||
|
|
||||||
|
#define TC_INT_MASK_REG TIMSK3 // interrupt timer mask register for timer(n)
|
||||||
|
#define TC_COUNTL TCNT3L // count high register for timer(n)
|
||||||
|
#define TC_COUNTH TCNT3H // count low register for timer(n)
|
||||||
|
|
||||||
|
/* Reciever setup */
|
||||||
|
#define TC_RX_COMPEN OCIE3C // interrupt enable for OCRnC (RX bit timer)
|
||||||
|
#define TC_RX_COMPH OCR3CH // OCRnC compare match high register
|
||||||
|
#define TC_RX_COMPL OCR3CL // OCRnC compare match high register
|
||||||
|
|
||||||
|
/* Transmitter setup */
|
||||||
|
#define TC_TX_COMPEN OCIE3B // interrupt enable for OCRnB (TX bit timer)
|
||||||
|
#define TC_TX_COMPH OCR3BH // OCRnB compare match high register
|
||||||
|
#define TC_TX_COMPL OCR3BL // OCRnB compare match low register
|
||||||
|
|
||||||
|
#define TC_CTRLB TCCR3B // timer(n) control register B
|
||||||
|
|
||||||
|
#define TC_INTFLAG_REG 0x18 // timer(n) interupt flag register
|
||||||
|
#define TC_TX_IF_BIT OCIE3B // timer(n) interrupt flag bit for OCRnB
|
||||||
|
#define TC_RX_IF_BIT OCIE3C // timer(n) interrupt flag bit for OCRnC
|
||||||
|
|
||||||
|
#endif
|
Loading…
Reference in New Issue