forked from mfulz_github/qmk_firmware
Rename software USART driver globals to make the code more in line with the rest of the XPLAINBridge project.
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79742c5d24
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f64e3db07a
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@ -39,7 +39,8 @@
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#include "SoftUART.h"
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#include "SoftUART.h"
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static uint8_t TX_BitsRemaining, TX_Data, RX_BitMask, RX_Data;
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static uint8_t TX_BitsRemaining, TX_Data;
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static uint8_t RX_BitMask, RX_Data;
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void SoftUART_Init(void)
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void SoftUART_Init(void)
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{
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{
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@ -50,16 +51,15 @@ void SoftUART_Init(void)
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EICRA = (1 << ISC01); // -ve edge
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EICRA = (1 << ISC01); // -ve edge
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EIMSK = (1 << INT0); // enable INT0 interrupt
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EIMSK = (1 << INT0); // enable INT0 interrupt
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TX_BitsRemaining = 0; // nothing to send
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STXPORT |= (1 << STX); // TX output
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STXPORT |= (1 << STX); // TX output
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STXDDR |= (1 << STX); // TX output
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STXDDR |= (1 << STX); // TX output
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SRXPORT |= (1 << SRX); // pullup on INT0
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SRXPORT |= (1 << SRX); // pullup on INT0
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}
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}
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/* ISR to detect the start of a bit being sent from the transmitter. */
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/* ISR to detect the start of a bit being sent to the software UART. */
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ISR(INT0_vect)
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ISR(INT0_vect)
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{
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{
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OCR2A = TCNT2 + (BIT_TIME / 8 * 3 / 2); // scan 1.5 bits after start
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OCR2A = TCNT2 + (uint16_t)((BIT_TIME / 8.0f) * 1.5f); // scan 1.5 bits after start
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RX_Data = 0; // clear bit storage
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RX_Data = 0; // clear bit storage
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RX_BitMask = (1 << 0); // bit mask
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RX_BitMask = (1 << 0); // bit mask
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@ -68,12 +68,12 @@ ISR(INT0_vect)
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if (!(SRXPIN & (1 << SRX))) // still low
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if (!(SRXPIN & (1 << SRX))) // still low
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{
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{
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TIMSK2 = (1 << OCIE2A) | (1 << OCIE2B); // wait for first bit
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TIMSK2 = (1 << OCIE2A) | (1 << OCIE2B); // wait for first bit
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EIMSK &= ~(1 << INT0);
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EIMSK &= ~(1 << INT0);
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}
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}
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}
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}
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/* ISR to manage the reception of bits to the transmitter. */
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/* ISR to manage the reception of bits to the software UART. */
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ISR(TIMER2_COMPA_vect)
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ISR(TIMER2_COMPA_vect)
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{
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{
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if (RX_BitMask)
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if (RX_BitMask)
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@ -89,13 +89,13 @@ ISR(TIMER2_COMPA_vect)
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{
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{
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RingBuffer_Insert(&UARTtoUSB_Buffer, RX_Data);
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RingBuffer_Insert(&UARTtoUSB_Buffer, RX_Data);
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TIMSK2 = (1 << OCIE2B); // enable tx and wait for start
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TIMSK2 = (1 << OCIE2B); // enable tx and wait for start
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EIMSK |= (1 << INT0); // enable START irq
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EIMSK |= (1 << INT0); // enable START irq
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EIFR = (1 << INTF0); // clear any pending
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EIFR = (1 << INTF0); // clear any pending
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}
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}
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}
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}
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/* ISR to manage the transmission of bits to the receiver. */
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/* ISR to manage the transmission of bits via the software UART. */
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ISR(TIMER2_COMPB_vect)
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ISR(TIMER2_COMPB_vect)
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{
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{
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OCR2B += BIT_TIME / 8; // next bit slice
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OCR2B += BIT_TIME / 8; // next bit slice
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@ -43,7 +43,7 @@
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/* Macros: */
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/* Macros: */
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#define BAUD 9600
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#define BAUD 9600
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#define BIT_TIME (uint16_t)((F_CPU + (BAUD / 2)) / BAUD)
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#define BIT_TIME (uint16_t)((F_CPU + (BAUD / 2.0f)) / BAUD)
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#define SRX PD0
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#define SRX PD0
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#define SRXPIN PIND
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#define SRXPIN PIND
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@ -156,7 +156,7 @@ void SetupHardware(void)
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_delay_ms(10);
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_delay_ms(10);
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/* Select the firmware mode based on the JTD pin's value */
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/* Select the firmware mode based on the JTD pin's value */
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CurrentFirmwareMode = (PINF & (1 << 7)) ? MODE_USART_BRIDGE : MODE_PDI_PROGRAMMER;
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CurrentFirmwareMode = MODE_USART_BRIDGE;//(PINF & (1 << 7)) ? MODE_USART_BRIDGE : MODE_PDI_PROGRAMMER;
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/* Re-enable JTAG debugging */
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/* Re-enable JTAG debugging */
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MCUCR &= ~(1 << JTD);
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MCUCR &= ~(1 << JTD);
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