forked from mfulz_github/qmk_firmware
471 lines
14 KiB
C
471 lines
14 KiB
C
/*
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LUFA Library
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Copyright (C) Dean Camera, 2010.
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dean [at] fourwalledcubicle [dot] com
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www.fourwalledcubicle.com
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*/
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/*
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Copyright 2010 Dean Camera (dean [at] fourwalledcubicle [dot] com)
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Permission to use, copy, modify, distribute, and sell this
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software and its documentation for any purpose is hereby granted
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without fee, provided that the above copyright notice appear in
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all copies and that both that the copyright notice and this
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permission notice and warranty disclaimer appear in supporting
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documentation, and that the name of the author not be used in
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advertising or publicity pertaining to distribution of the
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software without specific, written prior permission.
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The author disclaim all warranties with regard to this
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software, including all implied warranties of merchantability
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and fitness. In no event shall the author be liable for any
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special, indirect or consequential damages or any damages
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whatsoever resulting from loss of use, data or profits, whether
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in an action of contract, negligence or other tortious action,
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arising out of or in connection with the use or performance of
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this software.
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*/
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/** \file
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*
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* Target-related functions for the PDI Protocol decoder.
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*/
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#define INCLUDE_FROM_XPROGTARGET_C
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#include "XPROGTarget.h"
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#if defined(ENABLE_XPROG_PROTOCOL) || defined(__DOXYGEN__)
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/** Flag to indicate if the USART is currently in Tx or Rx mode. */
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volatile bool IsSending;
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#if !defined(XPROG_VIA_HARDWARE_USART)
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/** Software USART raw frame bits for transmission/reception. */
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volatile uint16_t SoftUSART_Data;
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/** Bits remaining to be sent or received via the software USART - set as a GPIOR for speed. */
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#define SoftUSART_BitCount GPIOR2
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/** ISR to manage the PDI software USART when bit-banged PDI USART mode is selected. */
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ISR(TIMER1_COMPA_vect, ISR_BLOCK)
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{
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/* Toggle CLOCK pin in a single cycle (see AVR datasheet) */
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BITBANG_PDICLOCK_PIN = BITBANG_PDICLOCK_MASK;
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/* If not sending or receiving, just exit */
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if (!(SoftUSART_BitCount))
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return;
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/* Check to see if we are at a rising or falling edge of the clock */
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if (BITBANG_PDICLOCK_PORT & BITBANG_PDICLOCK_MASK)
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{
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/* If at rising clock edge and we are in send mode, abort */
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if (IsSending)
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return;
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/* Wait for the start bit when receiving */
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if ((SoftUSART_BitCount == BITS_IN_USART_FRAME) && (BITBANG_PDIDATA_PIN & BITBANG_PDIDATA_MASK))
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return;
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/* Shift in the bit one less than the frame size in position, so that the start bit will eventually
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* be discarded leaving the data to be byte-aligned for quick access (subtract 9 as we are ORing to the MSB) */
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if (BITBANG_PDIDATA_PIN & BITBANG_PDIDATA_MASK)
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((uint8_t*)&SoftUSART_Data)[1] |= (1 << (BITS_IN_USART_FRAME - 9));
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SoftUSART_Data >>= 1;
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SoftUSART_BitCount--;
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}
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else
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{
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/* If at falling clock edge and we are in receive mode, abort */
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if (!IsSending)
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return;
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/* Set the data line to the next bit value */
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if (((uint8_t*)&SoftUSART_Data)[0] & 0x01)
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BITBANG_PDIDATA_PORT |= BITBANG_PDIDATA_MASK;
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else
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BITBANG_PDIDATA_PORT &= ~BITBANG_PDIDATA_MASK;
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SoftUSART_Data >>= 1;
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SoftUSART_BitCount--;
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}
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}
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/** ISR to manage the TPI software USART when bit-banged TPI USART mode is selected. */
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ISR(TIMER1_CAPT_vect, ISR_BLOCK)
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{
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/* Toggle CLOCK pin in a single cycle (see AVR datasheet) */
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BITBANG_TPICLOCK_PIN = BITBANG_TPICLOCK_MASK;
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/* If not sending or receiving, just exit */
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if (!(SoftUSART_BitCount))
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return;
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/* Check to see if we are at a rising or falling edge of the clock */
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if (BITBANG_TPICLOCK_PORT & BITBANG_TPICLOCK_MASK)
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{
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/* If at rising clock edge and we are in send mode, abort */
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if (IsSending)
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return;
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/* Wait for the start bit when receiving */
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if ((SoftUSART_BitCount == BITS_IN_USART_FRAME) && (BITBANG_TPIDATA_PIN & BITBANG_TPIDATA_MASK))
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return;
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/* Shift in the bit one less than the frame size in position, so that the start bit will eventually
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* be discarded leaving the data to be byte-aligned for quick access (subtract 9 as we are ORing to the MSB) */
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if (BITBANG_TPIDATA_PIN & BITBANG_TPIDATA_MASK)
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((uint8_t*)&SoftUSART_Data)[1] |= (1 << (BITS_IN_USART_FRAME - 9));
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SoftUSART_Data >>= 1;
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SoftUSART_BitCount--;
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}
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else
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{
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/* If at falling clock edge and we are in receive mode, abort */
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if (!IsSending)
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return;
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/* Set the data line to the next bit value */
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if (((uint8_t*)&SoftUSART_Data)[0] & 0x01)
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BITBANG_TPIDATA_PORT |= BITBANG_TPIDATA_MASK;
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else
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BITBANG_TPIDATA_PORT &= ~BITBANG_TPIDATA_MASK;
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SoftUSART_Data >>= 1;
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SoftUSART_BitCount--;
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}
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}
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#endif
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/** Enables the target's PDI interface, holding the target in reset until PDI mode is exited. */
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void XPROGTarget_EnableTargetPDI(void)
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{
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IsSending = false;
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#if defined(XPROG_VIA_HARDWARE_USART)
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/* Set Tx and XCK as outputs, Rx as input */
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DDRD |= (1 << 5) | (1 << 3);
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DDRD &= ~(1 << 2);
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/* Set DATA line high for at least 90ns to disable /RESET functionality */
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PORTD |= (1 << 3);
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_delay_us(1);
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/* Set up the synchronous USART for XMEGA communications -
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8 data bits, even parity, 2 stop bits */
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UBRR1 = (F_CPU / XPROG_HARDWARE_SPEED);
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UCSR1B = (1 << TXEN1);
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UCSR1C = (1 << UMSEL10) | (1 << UPM11) | (1 << USBS1) | (1 << UCSZ11) | (1 << UCSZ10) | (1 << UCPOL1);
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#else
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/* Set DATA and CLOCK lines to outputs */
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BITBANG_PDIDATA_DDR |= BITBANG_PDIDATA_MASK;
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BITBANG_PDICLOCK_DDR |= BITBANG_PDICLOCK_MASK;
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/* Set DATA line high for at least 90ns to disable /RESET functionality */
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BITBANG_PDIDATA_PORT |= BITBANG_PDIDATA_MASK;
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_delay_us(1);
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/* Fire timer compare channel A ISR to manage the software USART */
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OCR1A = BITS_BETWEEN_USART_CLOCKS;
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OCR1B = BITS_BETWEEN_USART_CLOCKS;
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TCCR1B = (1 << WGM12) | (1 << CS10);
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TIMSK1 = (1 << OCIE1A);
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#endif
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/* Send two BREAKs of 12 bits each to enable PDI interface (need at least 16 idle bits) */
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XPROGTarget_SendBreak();
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XPROGTarget_SendBreak();
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}
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/** Enables the target's TPI interface, holding the target in reset until TPI mode is exited. */
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void XPROGTarget_EnableTargetTPI(void)
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{
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IsSending = false;
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/* Set /RESET line low for at least 400ns to enable TPI functionality */
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AUX_LINE_DDR |= AUX_LINE_MASK;
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AUX_LINE_PORT &= ~AUX_LINE_MASK;
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_delay_us(1);
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#if defined(XPROG_VIA_HARDWARE_USART)
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/* Set Tx and XCK as outputs, Rx as input */
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DDRD |= (1 << 5) | (1 << 3);
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DDRD &= ~(1 << 2);
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/* Set up the synchronous USART for TINY communications -
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8 data bits, even parity, 2 stop bits */
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UBRR1 = (F_CPU / XPROG_HARDWARE_SPEED);
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UCSR1B = (1 << TXEN1);
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UCSR1C = (1 << UMSEL10) | (1 << UPM11) | (1 << USBS1) | (1 << UCSZ11) | (1 << UCSZ10) | (1 << UCPOL1);
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#else
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/* Set DATA and CLOCK lines to outputs */
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BITBANG_TPIDATA_DDR |= BITBANG_TPIDATA_MASK;
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BITBANG_TPICLOCK_DDR |= BITBANG_TPICLOCK_MASK;
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/* Set DATA line high for idle state */
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BITBANG_TPIDATA_PORT |= BITBANG_TPIDATA_MASK;
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/* Fire timer capture channel ISR to manage the software USART */
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ICR1 = BITS_BETWEEN_USART_CLOCKS;
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TCCR1B = (1 << WGM13) | (1 << WGM12) | (1 << CS10);
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TIMSK1 = (1 << ICIE1);
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#endif
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/* Send two BREAKs of 12 bits each to enable TPI interface (need at least 16 idle bits) */
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XPROGTarget_SendBreak();
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XPROGTarget_SendBreak();
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}
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/** Disables the target's PDI interface, exits programming mode and starts the target's application. */
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void XPROGTarget_DisableTargetPDI(void)
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{
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/* Switch to Rx mode to ensure that all pending transmissions are complete */
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XPROGTarget_SetRxMode();
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#if defined(XPROG_VIA_HARDWARE_USART)
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/* Turn off receiver and transmitter of the USART, clear settings */
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UCSR1A = ((1 << TXC1) | (1 << RXC1));
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UCSR1B = 0;
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UCSR1C = 0;
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/* Tristate all pins */
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DDRD &= ~((1 << 5) | (1 << 3));
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PORTD &= ~((1 << 5) | (1 << 3) | (1 << 2));
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#else
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/* Turn off software USART management timer */
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TCCR1B = 0;
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/* Set DATA and CLOCK lines to inputs */
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BITBANG_PDIDATA_DDR &= ~BITBANG_PDIDATA_MASK;
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BITBANG_PDICLOCK_DDR &= ~BITBANG_PDICLOCK_MASK;
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/* Tristate DATA and CLOCK lines */
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BITBANG_PDIDATA_PORT &= ~BITBANG_PDIDATA_MASK;
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BITBANG_PDICLOCK_PORT &= ~BITBANG_PDICLOCK_MASK;
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#endif
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}
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/** Disables the target's TPI interface, exits programming mode and starts the target's application. */
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void XPROGTarget_DisableTargetTPI(void)
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{
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/* Switch to Rx mode to ensure that all pending transmissions are complete */
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XPROGTarget_SetRxMode();
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#if defined(XPROG_VIA_HARDWARE_USART)
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/* Turn off receiver and transmitter of the USART, clear settings */
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UCSR1A |= (1 << TXC1) | (1 << RXC1);
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UCSR1B = 0;
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UCSR1C = 0;
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/* Set all USART lines as input, tristate */
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DDRD &= ~((1 << 5) | (1 << 3));
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PORTD &= ~((1 << 5) | (1 << 3) | (1 << 2));
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#else
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/* Turn off software USART management timer */
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TCCR1B = 0;
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/* Set DATA and CLOCK lines to inputs */
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BITBANG_TPIDATA_DDR &= ~BITBANG_TPIDATA_MASK;
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BITBANG_TPICLOCK_DDR &= ~BITBANG_TPICLOCK_MASK;
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/* Tristate DATA and CLOCK lines */
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BITBANG_TPIDATA_PORT &= ~BITBANG_TPIDATA_MASK;
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BITBANG_TPICLOCK_PORT &= ~BITBANG_TPICLOCK_MASK;
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#endif
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/* Tristate target /RESET line */
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AUX_LINE_DDR &= ~AUX_LINE_MASK;
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AUX_LINE_PORT &= ~AUX_LINE_MASK;
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}
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/** Sends a byte via the USART.
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*
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* \param[in] Byte Byte to send through the USART
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*/
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void XPROGTarget_SendByte(const uint8_t Byte)
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{
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/* Switch to Tx mode if currently in Rx mode */
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if (!(IsSending))
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XPROGTarget_SetTxMode();
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#if defined(XPROG_VIA_HARDWARE_USART)
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/* Wait until there is space in the hardware Tx buffer before writing */
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while (!(UCSR1A & (1 << UDRE1)));
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UCSR1A |= (1 << TXC1);
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UDR1 = Byte;
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#else
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/* Calculate the new USART frame data here while while we wait for a previous byte (if any) to finish sending */
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uint16_t NewUSARTData = ((1 << 11) | (1 << 10) | (0 << 9) | ((uint16_t)Byte << 1) | (0 << 0));
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/* Compute Even parity - while a bit is still set, chop off lowest bit and toggle parity bit */
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uint8_t ParityData = Byte;
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while (ParityData)
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{
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NewUSARTData ^= (1 << 9);
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ParityData &= (ParityData - 1);
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}
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/* Wait until transmitter is idle before writing new data */
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while (SoftUSART_BitCount);
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/* Data shifted out LSB first, START DATA PARITY STOP STOP */
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SoftUSART_Data = NewUSARTData;
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SoftUSART_BitCount = BITS_IN_USART_FRAME;
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#endif
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}
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/** Receives a byte via the software USART, blocking until data is received.
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*
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* \return Received byte from the USART
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*/
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uint8_t XPROGTarget_ReceiveByte(void)
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{
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/* Switch to Rx mode if currently in Tx mode */
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if (IsSending)
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XPROGTarget_SetRxMode();
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#if defined(XPROG_VIA_HARDWARE_USART)
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/* Wait until a byte has been received before reading */
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while (!(UCSR1A & (1 << RXC1)) && TimeoutMSRemaining)
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{
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/* Manage software timeout */
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if (TIFR0 & (1 << OCF0A))
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{
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TIFR0 |= (1 << OCF0A);
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TimeoutMSRemaining--;
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}
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}
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return UDR1;
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#else
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/* Wait until a byte has been received before reading */
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SoftUSART_BitCount = BITS_IN_USART_FRAME;
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while (SoftUSART_BitCount && TimeoutMSRemaining)
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{
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/* Manage software timeout */
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if (TIFR0 & (1 << OCF0A))
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{
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TIFR0 |= (1 << OCF0A);
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TimeoutMSRemaining--;
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}
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}
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if (TimeoutMSRemaining)
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TimeoutMSRemaining = COMMAND_TIMEOUT_MS;
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/* Throw away the parity and stop bits to leave only the data (start bit is already discarded) */
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return (uint8_t)SoftUSART_Data;
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#endif
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}
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/** Sends a BREAK via the USART to the attached target, consisting of a full frame of idle bits. */
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void XPROGTarget_SendBreak(void)
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{
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/* Switch to Tx mode if currently in Rx mode */
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if (!(IsSending))
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XPROGTarget_SetTxMode();
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#if defined(XPROG_VIA_HARDWARE_USART)
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/* Need to do nothing for a full frame to send a BREAK */
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for (uint8_t i = 0; i < BITS_IN_USART_FRAME; i++)
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{
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/* Wait for a full cycle of the clock */
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while (PIND & (1 << 5));
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while (!(PIND & (1 << 5)));
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}
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#else
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while (SoftUSART_BitCount);
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/* Need to do nothing for a full frame to send a BREAK */
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SoftUSART_Data = 0x0FFF;
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SoftUSART_BitCount = BITS_IN_USART_FRAME;
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#endif
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}
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static void XPROGTarget_SetTxMode(void)
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{
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#if defined(XPROG_VIA_HARDWARE_USART)
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/* Wait for a full cycle of the clock */
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while (PIND & (1 << 5));
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while (!(PIND & (1 << 5)));
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PORTD |= (1 << 3);
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DDRD |= (1 << 3);
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UCSR1B &= ~(1 << RXEN1);
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UCSR1B |= (1 << TXEN1);
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IsSending = true;
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#else
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while (SoftUSART_BitCount);
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/* Wait for a full cycle of the clock */
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SoftUSART_Data = 0x0001;
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SoftUSART_BitCount = 1;
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while (SoftUSART_BitCount);
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if (XPROG_SelectedProtocol == XPRG_PROTOCOL_PDI)
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{
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BITBANG_PDIDATA_PORT |= BITBANG_PDIDATA_MASK;
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BITBANG_PDIDATA_DDR |= BITBANG_PDIDATA_MASK;
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}
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else
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{
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BITBANG_TPIDATA_PORT |= BITBANG_TPIDATA_MASK;
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BITBANG_TPIDATA_DDR |= BITBANG_TPIDATA_MASK;
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}
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#endif
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IsSending = true;
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}
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static void XPROGTarget_SetRxMode(void)
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{
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#if defined(XPROG_VIA_HARDWARE_USART)
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while (!(UCSR1A & (1 << TXC1)));
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UCSR1A |= (1 << TXC1);
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UCSR1B &= ~(1 << TXEN1);
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UCSR1B |= (1 << RXEN1);
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DDRD &= ~(1 << 3);
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PORTD &= ~(1 << 3);
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#else
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while (SoftUSART_BitCount);
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if (XPROG_SelectedProtocol == XPRG_PROTOCOL_PDI)
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{
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BITBANG_PDIDATA_DDR &= ~BITBANG_PDIDATA_MASK;
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BITBANG_PDIDATA_PORT &= ~BITBANG_PDIDATA_MASK;
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}
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else
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{
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BITBANG_TPIDATA_DDR &= ~BITBANG_TPIDATA_MASK;
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BITBANG_TPIDATA_PORT &= ~BITBANG_TPIDATA_MASK;
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}
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/* Wait until DATA line has been pulled up to idle by the target */
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while (!(BITBANG_PDIDATA_PIN & BITBANG_PDIDATA_MASK) && TimeoutMSRemaining)
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{
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/* Manage software timeout */
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if (TIFR0 & (1 << OCF0A))
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{
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TIFR0 |= (1 << OCF0A);
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TimeoutMSRemaining--;
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}
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}
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#endif
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if (TimeoutMSRemaining)
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TimeoutMSRemaining = COMMAND_TIMEOUT_MS;
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IsSending = false;
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}
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#endif
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