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	Minor documentation improvements.
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				| @ -100,61 +100,61 @@ | ||||
| 		/* Macros: */ | ||||
| 			/** \name SPI Prescaler Configuration Masks */ | ||||
| 			//@{
 | ||||
| 			/** SPI prescaler mask for \c SPI_Init(). Divides the system clock by a factor of 2. */ | ||||
| 			/** SPI prescaler mask for \ref SPI_Init(). Divides the system clock by a factor of 2. */ | ||||
| 			#define SPI_SPEED_FCPU_DIV_2           SPI_USE_DOUBLESPEED | ||||
| 
 | ||||
| 			/** SPI prescaler mask for \c SPI_Init(). Divides the system clock by a factor of 4. */ | ||||
| 			/** SPI prescaler mask for \ref SPI_Init(). Divides the system clock by a factor of 4. */ | ||||
| 			#define SPI_SPEED_FCPU_DIV_4           0 | ||||
| 
 | ||||
| 			/** SPI prescaler mask for \c SPI_Init(). Divides the system clock by a factor of 8. */ | ||||
| 			/** SPI prescaler mask for \ref SPI_Init(). Divides the system clock by a factor of 8. */ | ||||
| 			#define SPI_SPEED_FCPU_DIV_8           (SPI_USE_DOUBLESPEED | (1 << SPR0)) | ||||
| 
 | ||||
| 			/** SPI prescaler mask for \c SPI_Init(). Divides the system clock by a factor of 16. */ | ||||
| 			/** SPI prescaler mask for \ref SPI_Init(). Divides the system clock by a factor of 16. */ | ||||
| 			#define SPI_SPEED_FCPU_DIV_16          (1 << SPR0) | ||||
| 
 | ||||
| 			/** SPI prescaler mask for \c SPI_Init(). Divides the system clock by a factor of 32. */ | ||||
| 			/** SPI prescaler mask for \ref SPI_Init(). Divides the system clock by a factor of 32. */ | ||||
| 			#define SPI_SPEED_FCPU_DIV_32          (SPI_USE_DOUBLESPEED | (1 << SPR1)) | ||||
| 
 | ||||
| 			/** SPI prescaler mask for \c SPI_Init(). Divides the system clock by a factor of 64. */ | ||||
| 			/** SPI prescaler mask for \ref SPI_Init(). Divides the system clock by a factor of 64. */ | ||||
| 			#define SPI_SPEED_FCPU_DIV_64          (SPI_USE_DOUBLESPEED | (1 << SPR1) | (1 << SPR0)) | ||||
| 
 | ||||
| 			/** SPI prescaler mask for \c SPI_Init(). Divides the system clock by a factor of 128. */ | ||||
| 			/** SPI prescaler mask for \ref SPI_Init(). Divides the system clock by a factor of 128. */ | ||||
| 			#define SPI_SPEED_FCPU_DIV_128         ((1 << SPR1) | (1 << SPR0)) | ||||
| 			//@}
 | ||||
| 
 | ||||
| 			/** \name SPI SCK Polarity Configuration Masks */ | ||||
| 			//@{
 | ||||
| 			/** SPI clock polarity mask for \c SPI_Init(). Indicates that the SCK should lead on the rising edge. */ | ||||
| 			/** SPI clock polarity mask for \ref SPI_Init(). Indicates that the SCK should lead on the rising edge. */ | ||||
| 			#define SPI_SCK_LEAD_RISING            (0 << CPOL) | ||||
| 
 | ||||
| 			/** SPI clock polarity mask for \c SPI_Init(). Indicates that the SCK should lead on the falling edge. */ | ||||
| 			/** SPI clock polarity mask for \ref SPI_Init(). Indicates that the SCK should lead on the falling edge. */ | ||||
| 			#define SPI_SCK_LEAD_FALLING           (1 << CPOL) | ||||
| 			//@}
 | ||||
| 
 | ||||
| 			/** \name SPI Sample Edge Configuration Masks */ | ||||
| 			//@{
 | ||||
| 			/** SPI data sample mode mask for \c SPI_Init(). Indicates that the data should sampled on the leading edge. */ | ||||
| 			/** SPI data sample mode mask for \ref SPI_Init(). Indicates that the data should sampled on the leading edge. */ | ||||
| 			#define SPI_SAMPLE_LEADING             (0 << CPHA) | ||||
| 
 | ||||
| 			/** SPI data sample mode mask for \c SPI_Init(). Indicates that the data should be sampled on the trailing edge. */ | ||||
| 			/** SPI data sample mode mask for \ref SPI_Init(). Indicates that the data should be sampled on the trailing edge. */ | ||||
| 			#define SPI_SAMPLE_TRAILING            (1 << CPHA) | ||||
| 			//@}
 | ||||
| 
 | ||||
| 			/** \name SPI Data Ordering Configuration Masks */ | ||||
| 			//@{
 | ||||
| 			/** SPI data order mask for \c SPI_Init(). Indicates that data should be shifted out MSB first. */ | ||||
| 			/** SPI data order mask for \ref SPI_Init(). Indicates that data should be shifted out MSB first. */ | ||||
| 			#define SPI_ORDER_MSB_FIRST            (0 << DORD) | ||||
| 
 | ||||
| 			/** SPI data order mask for \c SPI_Init(). Indicates that data should be shifted out LSB first. */ | ||||
| 			/** SPI data order mask for \ref SPI_Init(). Indicates that data should be shifted out LSB first. */ | ||||
| 			#define SPI_ORDER_LSB_FIRST            (1 << DORD) | ||||
| 			//@}
 | ||||
| 
 | ||||
| 			/** \name SPI Mode Configuration Masks */ | ||||
| 			//@{
 | ||||
| 			/** SPI mode mask for \c SPI_Init(). Indicates that the SPI interface should be initialized into slave mode. */ | ||||
| 			/** SPI mode mask for \ref SPI_Init(). Indicates that the SPI interface should be initialized into slave mode. */ | ||||
| 			#define SPI_MODE_SLAVE                 (0 << MSTR) | ||||
| 
 | ||||
| 			/** SPI mode mask for \c SPI_Init(). Indicates that the SPI interface should be initialized into master mode. */ | ||||
| 			/** SPI mode mask for \ref SPI_Init(). Indicates that the SPI interface should be initialized into master mode. */ | ||||
| 			#define SPI_MODE_MASTER                (1 << MSTR) | ||||
| 			//@}
 | ||||
| 
 | ||||
|  | ||||
| @ -29,7 +29,7 @@ | ||||
| */ | ||||
| 
 | ||||
| /** \file
 | ||||
|  *  \brief Serial USART Master SPI Mode Peripheral Driver (XMEGA) | ||||
|  *  \brief Master SPI Mode Serial USART Peripheral Driver (XMEGA) | ||||
|  * | ||||
|  *  On-chip Master SPI mode USART driver for the XMEGA AVR microcontrollers. | ||||
|  * | ||||
| @ -38,7 +38,7 @@ | ||||
|  */ | ||||
| 
 | ||||
| /** \ingroup Group_SerialSPI
 | ||||
|  *  \defgroup Group_SerialSPI_AVR8 Serial USART Peripheral Driver (AVR8) | ||||
|  *  \defgroup Group_SerialSPI_AVR8 Master SPI Mode Serial USART Peripheral Driver (AVR8) | ||||
|  * | ||||
|  *  \section Sec_ModDescription Module Description | ||||
|  *  On-chip serial USART driver for the 8-bit AVR8 microcontrollers. | ||||
| @ -98,28 +98,28 @@ | ||||
| 		/* Macros: */ | ||||
| 			/** \name SPI SCK Polarity Configuration Masks */ | ||||
| 			//@{
 | ||||
| 			/** SPI clock polarity mask for \c SPI_Init(). Indicates that the SCK should lead on the rising edge. */ | ||||
| 			/** SPI clock polarity mask for \ref SPI_Init(). Indicates that the SCK should lead on the rising edge. */ | ||||
| 			#define USART_SPI_SCK_LEAD_RISING            (0 << UCPOL) | ||||
| 
 | ||||
| 			/** SPI clock polarity mask for \c SPI_Init(). Indicates that the SCK should lead on the falling edge. */ | ||||
| 			/** SPI clock polarity mask for \ref SPI_Init(). Indicates that the SCK should lead on the falling edge. */ | ||||
| 			#define USART_SPI_SCK_LEAD_FALLING           (1 << UCPOL) | ||||
| 			//@}
 | ||||
| 
 | ||||
| 			/** \name SPI Sample Edge Configuration Masks */ | ||||
| 			//@{
 | ||||
| 			/** SPI data sample mode mask for \c SerialSPI_Init(). Indicates that the data should sampled on the leading edge. */ | ||||
| 			/** SPI data sample mode mask for \ref SerialSPI_Init(). Indicates that the data should sampled on the leading edge. */ | ||||
| 			#define USART_SPI_SAMPLE_LEADING             (0 << UPCHA) | ||||
| 
 | ||||
| 			/** SPI data sample mode mask for \c SerialSPI_Init(). Indicates that the data should be sampled on the trailing edge. */ | ||||
| 			/** SPI data sample mode mask for \ref SerialSPI_Init(). Indicates that the data should be sampled on the trailing edge. */ | ||||
| 			#define USART_SPI_SAMPLE_TRAILING            (1 << UPCHA) | ||||
| 			//@}
 | ||||
| 
 | ||||
| 			/** \name SPI Data Ordering Configuration Masks */ | ||||
| 			//@{
 | ||||
| 			/** SPI data order mask for \c Serial_SPIInit(). Indicates that data should be shifted out MSB first. */ | ||||
| 			/** SPI data order mask for \ref SerialSPI_Init(). Indicates that data should be shifted out MSB first. */ | ||||
| 			#define USART_SPI_ORDER_MSB_FIRST            (0 << UDORD) | ||||
| 
 | ||||
| 			/** SPI data order mask for \c Serial_SPIInit(). Indicates that data should be shifted out LSB first. */ | ||||
| 			/** SPI data order mask for \ref SerialSPI_Init(). Indicates that data should be shifted out LSB first. */ | ||||
| 			#define USART_SPI_ORDER_LSB_FIRST            (1 << UDORD) | ||||
| 			//@}			
 | ||||
| 
 | ||||
|  | ||||
| @ -97,61 +97,61 @@ | ||||
| 		/* Macros: */ | ||||
| 			/** \name SPI Prescaler Configuration Masks */ | ||||
| 			//@{
 | ||||
| 			/** SPI prescaler mask for \c SPI_Init(). Divides the system clock by a factor of 2. */ | ||||
| 			/** SPI prescaler mask for \ref SPI_Init(). Divides the system clock by a factor of 2. */ | ||||
| 			#define SPI_SPEED_FCPU_DIV_2           SPI_USE_DOUBLESPEED | ||||
| 
 | ||||
| 			/** SPI prescaler mask for \c SPI_Init(). Divides the system clock by a factor of 4. */ | ||||
| 			/** SPI prescaler mask for \ref SPI_Init(). Divides the system clock by a factor of 4. */ | ||||
| 			#define SPI_SPEED_FCPU_DIV_4           0 | ||||
| 
 | ||||
| 			/** SPI prescaler mask for \c SPI_Init(). Divides the system clock by a factor of 8. */ | ||||
| 			/** SPI prescaler mask for \ref SPI_Init(). Divides the system clock by a factor of 8. */ | ||||
| 			#define SPI_SPEED_FCPU_DIV_8           (SPI_USE_DOUBLESPEED | (1 << SPI_PRESCALER_gp)) | ||||
| 
 | ||||
| 			/** SPI prescaler mask for \c SPI_Init(). Divides the system clock by a factor of 16. */ | ||||
| 			/** SPI prescaler mask for \ref SPI_Init(). Divides the system clock by a factor of 16. */ | ||||
| 			#define SPI_SPEED_FCPU_DIV_16          (1 << SPI_PRESCALER_gp) | ||||
| 
 | ||||
| 			/** SPI prescaler mask for \c SPI_Init(). Divides the system clock by a factor of 32. */ | ||||
| 			/** SPI prescaler mask for \ref SPI_Init(). Divides the system clock by a factor of 32. */ | ||||
| 			#define SPI_SPEED_FCPU_DIV_32          (SPI_USE_DOUBLESPEED | (2 << SPI_PRESCALER_gp)) | ||||
| 
 | ||||
| 			/** SPI prescaler mask for \c SPI_Init(). Divides the system clock by a factor of 64. */ | ||||
| 			/** SPI prescaler mask for \ref SPI_Init(). Divides the system clock by a factor of 64. */ | ||||
| 			#define SPI_SPEED_FCPU_DIV_64          (2 << SPI_PRESCALER_gp) | ||||
| 
 | ||||
| 			/** SPI prescaler mask for \c SPI_Init(). Divides the system clock by a factor of 128. */ | ||||
| 			/** SPI prescaler mask for \ref SPI_Init(). Divides the system clock by a factor of 128. */ | ||||
| 			#define SPI_SPEED_FCPU_DIV_128         (3 << SPI_PRESCALER_gp) | ||||
| 			//@}
 | ||||
| 
 | ||||
| 			/** \name SPI SCK Polarity Configuration Masks */ | ||||
| 			//@{
 | ||||
| 			/** SPI clock polarity mask for \c SPI_Init(). Indicates that the SCK should lead on the rising edge. */ | ||||
| 			/** SPI clock polarity mask for \ref SPI_Init(). Indicates that the SCK should lead on the rising edge. */ | ||||
| 			#define SPI_SCK_LEAD_RISING            0 | ||||
| 
 | ||||
| 			/** SPI clock polarity mask for \c SPI_Init(). Indicates that the SCK should lead on the falling edge. */ | ||||
| 			/** SPI clock polarity mask for \ref SPI_Init(). Indicates that the SCK should lead on the falling edge. */ | ||||
| 			#define SPI_SCK_LEAD_FALLING           SPI_MODE1_bm | ||||
| 			//@}
 | ||||
| 
 | ||||
| 			/** \name SPI Sample Edge Configuration Masks */ | ||||
| 			//@{
 | ||||
| 			/** SPI data sample mode mask for \c SPI_Init(). Indicates that the data should sampled on the leading edge. */ | ||||
| 			/** SPI data sample mode mask for \ref SPI_Init(). Indicates that the data should sampled on the leading edge. */ | ||||
| 			#define SPI_SAMPLE_LEADING             0 | ||||
| 
 | ||||
| 			/** SPI data sample mode mask for \c SPI_Init(). Indicates that the data should be sampled on the trailing edge. */ | ||||
| 			/** SPI data sample mode mask for \ref SPI_Init(). Indicates that the data should be sampled on the trailing edge. */ | ||||
| 			#define SPI_SAMPLE_TRAILING            SPI_MODE0_bm | ||||
| 			//@}
 | ||||
| 
 | ||||
| 			/** \name SPI Data Ordering Configuration Masks */ | ||||
| 			//@{
 | ||||
| 			/** SPI data order mask for \c SPI_Init(). Indicates that data should be shifted out MSB first. */ | ||||
| 			/** SPI data order mask for \ref SPI_Init(). Indicates that data should be shifted out MSB first. */ | ||||
| 			#define SPI_ORDER_MSB_FIRST            0 | ||||
| 
 | ||||
| 			/** SPI data order mask for \c SPI_Init(). Indicates that data should be shifted out LSB first. */ | ||||
| 			/** SPI data order mask for \ref SPI_Init(). Indicates that data should be shifted out LSB first. */ | ||||
| 			#define SPI_ORDER_LSB_FIRST            SPI_DORD_bm | ||||
| 			//@}
 | ||||
| 
 | ||||
| 			/** \name SPI Mode Configuration Masks */ | ||||
| 			//@{
 | ||||
| 			/** SPI mode mask for \c SPI_Init(). Indicates that the SPI interface should be initialized into slave mode. */ | ||||
| 			/** SPI mode mask for \ref SPI_Init(). Indicates that the SPI interface should be initialized into slave mode. */ | ||||
| 			#define SPI_MODE_SLAVE                 0 | ||||
| 
 | ||||
| 			/** SPI mode mask for \c SPI_Init(). Indicates that the SPI interface should be initialized into master mode. */ | ||||
| 			/** SPI mode mask for \ref SPI_Init(). Indicates that the SPI interface should be initialized into master mode. */ | ||||
| 			#define SPI_MODE_MASTER                SPI_MASTER_bm | ||||
| 			//@}
 | ||||
| 
 | ||||
|  | ||||
| @ -29,7 +29,7 @@ | ||||
| */ | ||||
| 
 | ||||
| /** \file
 | ||||
|  *  \brief Serial USART Master SPI Mode Peripheral Driver (XMEGA) | ||||
|  *  \brief Master SPI Mode Serial USART Peripheral Driver (XMEGA) | ||||
|  * | ||||
|  *  On-chip Master SPI mode USART driver for the XMEGA AVR microcontrollers. | ||||
|  * | ||||
| @ -38,7 +38,7 @@ | ||||
|  */ | ||||
| 
 | ||||
| /** \ingroup Group_SerialSPI
 | ||||
|  *  \defgroup Group_SerialSPI_XMEGA Serial USART Peripheral Driver (XMEGA) | ||||
|  *  \defgroup Group_SerialSPI_XMEGA Master SPI Mode Serial USART Peripheral Driver (XMEGA) | ||||
|  * | ||||
|  *  \section Sec_ModDescription Module Description | ||||
|  *  On-chip serial USART driver for the XMEGA AVR microcontrollers. | ||||
| @ -52,12 +52,12 @@ | ||||
|  * | ||||
|  *  \code | ||||
|  *      // Initialize the Master SPI mode USART driver before first use, with 1Mbit baud
 | ||||
|  *      SerialSPI_Init(&USARTD, (USART_SPI_SCK_LEAD_RISING | SPI_SAMPLE_LEADING | SPI_ORDER_MSB_FIRST), 1000000); | ||||
|  *      SerialSPI_Init(&USARTD0, (USART_SPI_SCK_LEAD_RISING | SPI_SAMPLE_LEADING | SPI_ORDER_MSB_FIRST), 1000000); | ||||
|  * | ||||
|  *      // Send several bytes, ignoring the returned data
 | ||||
|  *      SerialSPI_SendByte(&USARTD, 0x01); | ||||
|  *      SerialSPI_SendByte(&USARTD, 0x02); | ||||
|  *      SerialSPI_SendByte(&USARTD, 0x03); | ||||
|  *      SerialSPI_SendByte(&USARTD0, 0x01); | ||||
|  *      SerialSPI_SendByte(&USARTD0, 0x02); | ||||
|  *      SerialSPI_SendByte(&USARTD0, 0x03); | ||||
|  * | ||||
|  *      // Receive several bytes, sending a dummy 0x00 byte each time
 | ||||
|  *      uint8_t Byte1 = SerialSPI_ReceiveByte(&USARTD); | ||||
| @ -65,7 +65,7 @@ | ||||
|  *      uint8_t Byte3 = SerialSPI_ReceiveByte(&USARTD); | ||||
|  * | ||||
|  *      // Send a byte, and store the received byte from the same transaction
 | ||||
|  *      uint8_t ResponseByte = SerialSPI_TransferByte(&USARTD, 0xDC); | ||||
|  *      uint8_t ResponseByte = SerialSPI_TransferByte(&USARTD0, 0xDC); | ||||
|  *  \endcode | ||||
|  * | ||||
|  *  @{ | ||||
| @ -98,25 +98,25 @@ | ||||
| 		/* Macros: */ | ||||
| 			/** \name SPI SCK Polarity Configuration Masks */ | ||||
| 			//@{
 | ||||
| 			/** SPI clock polarity mask for \c SerialSPI_Init(). Indicates that the SCK should lead on the rising edge. */ | ||||
| 			/** SPI clock polarity mask for \ref SerialSPI_Init(). Indicates that the SCK should lead on the rising edge. */ | ||||
| 			#define USART_SPI_SCK_LEAD_RISING      0 | ||||
| 			//@}
 | ||||
| 
 | ||||
| 			/** \name SPI Sample Edge Configuration Masks */ | ||||
| 			//@{
 | ||||
| 			/** SPI data sample mode mask for \c SerialSPI_Init(). Indicates that the data should sampled on the leading edge. */ | ||||
| 			/** SPI data sample mode mask for \ref SerialSPI_Init(). Indicates that the data should sampled on the leading edge. */ | ||||
| 			#define USART_SPI_SAMPLE_LEADING       0 | ||||
| 
 | ||||
| 			/** SPI data sample mode mask for \c SerialSPI_Init(). Indicates that the data should be sampled on the trailing edge. */ | ||||
| 			/** SPI data sample mode mask for \ref SerialSPI_Init(). Indicates that the data should be sampled on the trailing edge. */ | ||||
| 			#define USART_SPI_SAMPLE_TRAILING      USART_UPCHA_bm | ||||
| 			//@}
 | ||||
| 
 | ||||
| 			/** \name SPI Data Ordering Configuration Masks */ | ||||
| 			//@{
 | ||||
| 			/** SPI data order mask for \c Serial_SPIInit(). Indicates that data should be shifted out MSB first. */ | ||||
| 			/** SPI data order mask for \ref SerialSPI_Init(). Indicates that data should be shifted out MSB first. */ | ||||
| 			#define USART_SPI_ORDER_MSB_FIRST      0 | ||||
| 
 | ||||
| 			/** SPI data order mask for \c Serial_SPIInit(). Indicates that data should be shifted out LSB first. */ | ||||
| 			/** SPI data order mask for \ref SerialSPI_Init(). Indicates that data should be shifted out LSB first. */ | ||||
| 			#define USART_SPI_ORDER_LSB_FIRST      USART_UDORD_bm | ||||
| 			//@}			
 | ||||
| 
 | ||||
|  | ||||
| @ -52,13 +52,13 @@ | ||||
|  * | ||||
|  *  \code | ||||
|  *      // Initialize the serial USART driver before first use, with 9600 baud (and no double-speed mode)
 | ||||
|  *      Serial_Init(&USARTD, 9600, false); | ||||
|  *      Serial_Init(&USARTD0, 9600, false); | ||||
|  * | ||||
|  *      // Send a string through the USART
 | ||||
|  *      Serial_TxString(&USARTD, "Test String\r\n"); | ||||
|  *      Serial_TxString(&USARTD0, "Test String\r\n"); | ||||
|  * | ||||
|  *      // Receive a byte through the USART
 | ||||
|  *      uint8_t DataByte = Serial_RxByte(&USARTD); | ||||
|  *      uint8_t DataByte = Serial_RxByte(&USARTD0); | ||||
|  *  \endcode | ||||
|  * | ||||
|  *  @{ | ||||
|  | ||||
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