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Add glitch protection to the software UART in the XPLAINBridge project code, so that very short glitches on the RX line don't cause a frame reception to occur.

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This commit is contained in:
Dean Camera 2010-07-12 02:23:11 +00:00
parent 229935184b
commit 3fd246041b
2 changed files with 14 additions and 8 deletions
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20
Projects/XPLAINBridge/Lib/SoftUART.c
View File

@ -76,15 +76,21 @@ void SoftUART_Init(void)
/** ISR to detect the start of a bit being sent to the software UART. */ /** ISR to detect the start of a bit being sent to the software UART. */
ISR(INT0_vect, ISR_BLOCK) ISR(INT0_vect, ISR_BLOCK)
{ {
/* Reset and start the reception timer */
TCNT1 = 0;
TCCR1B = ((1 << CS10) | (1 << WGM12));
/* Reset the number of reception bits remaining counter */ /* Reset the number of reception bits remaining counter */
RX_BitsRemaining = 8; RX_BitsRemaining = 8;
/* Reset the bit reception timer */
TCNT1 = 0;
/* Disable start bit detection ISR while the next byte is received */ /* Check to see that the pin is still low (prevents glitches from starting a frame reception) */
EIMSK = 0; if (!(SRXPIN & (1 << SRX)))
{
/* Disable start bit detection ISR while the next byte is received */
EIMSK = 0;
/* Start the reception timer */
TCCR1B = ((1 << CS10) | (1 << WGM12));
}
} }
/** ISR to manage the reception of bits to the software UART. */ /** ISR to manage the reception of bits to the software UART. */
@ -133,7 +139,7 @@ ISR(TIMER3_COMPA_vect, ISR_NOBLOCK)
TX_Data >>= 1; TX_Data >>= 1;
TX_BitsRemaining--; TX_BitsRemaining--;
} }
else if (USBtoUART_Buffer.Count) else if (USBtoUART_Buffer.Count && !(RX_BitsRemaining))
{ {
/* Start bit - TX line low */ /* Start bit - TX line low */
STXPORT &= ~(1 << STX); STXPORT &= ~(1 << STX);

2
Projects/XPLAINBridge/XPLAINBridge.c
View File

@ -180,7 +180,7 @@ void EVENT_USB_Device_ConfigurationChanged(void)
{ {
EndpointConfigSuccess &= CDC_Device_ConfigureEndpoints(&VirtualSerial_CDC_Interface); EndpointConfigSuccess &= CDC_Device_ConfigureEndpoints(&VirtualSerial_CDC_Interface);
/* Configure the UART flush timer */ /* Configure the UART flush timer - run at FCPU/1024 for maximum interval before overflow */
TCCR0B = ((1 << CS02) | (1 << CS00)); TCCR0B = ((1 << CS02) | (1 << CS00));
} }
else else