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https://github.com/mfulz/qmk_firmware.git
synced 2025-11-04 07:12:33 +01:00
Use the PDI REPEAT instruction in the PDI programmer code to reduce protocol overhead and greatly improve transfer throughput. Switch bit-bang USART in the AVRISP project to Timer 1, so that Timer 0 can be used for hardware timeouts while waiting for the NVM bus or controller to become ready.
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Dean Camera
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@ -40,8 +40,10 @@
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void NVMTarget_SendNVMRegAddress(uint8_t Register)
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{
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/* Determine the absolute register address from the NVM base memory address and the NVM register address */
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uint32_t Address = XPROG_Param_NVMBase | Register;
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/* Send the calculated 32-bit address to the target, LSB first */
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PDITarget_SendByte(Address & 0xFF);
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PDITarget_SendByte(Address >> 8);
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PDITarget_SendByte(Address >> 16);
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@ -50,40 +52,32 @@ void NVMTarget_SendNVMRegAddress(uint8_t Register)
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void NVMTarget_SendAddress(uint32_t AbsoluteAddress)
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{
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/* Send the given 32-bit address to the target, LSB first */
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PDITarget_SendByte(AbsoluteAddress & 0xFF);
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PDITarget_SendByte(AbsoluteAddress >> 8);
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PDITarget_SendByte(AbsoluteAddress >> 16);
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PDITarget_SendByte(AbsoluteAddress >> 24);
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}
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bool NVMTarget_WaitWhileNVMBusBusy(void)
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bool NVMTarget_WaitWhileNVMControllerBusy(void)
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{
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uint8_t AttemptsRemaining = 255;
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TCNT0 = 0;
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/* Poll the STATUS register to check to see if NVM access has been enabled */
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while (AttemptsRemaining--)
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/* Poll the NVM STATUS register while the NVM controller is busy */
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while (TCNT0 < NVM_BUSY_TIMEOUT_MS)
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{
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PDITarget_SendByte(PDI_CMD_LDCS | PDI_STATUS_REG);
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if (PDITarget_ReceiveByte() & PDI_STATUS_NVM)
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/* Send a LDS command to read the NVM STATUS register to check the BUSY flag */
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PDITarget_SendByte(PDI_CMD_LDS | (PDI_DATSIZE_4BYTES << 2));
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NVMTarget_SendNVMRegAddress(NVM_REG_STATUS);
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/* Check to see if the BUSY flag is still set */
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if (!(PDITarget_ReceiveByte() & (1 << 7)))
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return true;
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}
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return false;
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}
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void NVMTarget_WaitWhileNVMControllerBusy(void)
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{
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/* Poll the NVM STATUS register while the NVM controller is busy */
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for (;;)
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{
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PDITarget_SendByte(PDI_CMD_LDS | (PDI_DATSIZE_4BYTES << 2));
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NVMTarget_SendNVMRegAddress(NVM_REG_STATUS);
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if (!(PDITarget_ReceiveByte() & (1 << 7)))
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return;
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}
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}
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uint32_t NVMTarget_GetMemoryCRC(uint8_t MemoryCommand)
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{
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uint32_t MemoryCRC;
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@ -101,18 +95,20 @@ uint32_t NVMTarget_GetMemoryCRC(uint8_t MemoryCommand)
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PDITarget_SendByte(1 << 0);
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/* Wait until the NVM bus and controller is no longer busy */
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NVMTarget_WaitWhileNVMBusBusy();
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PDITarget_WaitWhileNVMBusBusy();
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NVMTarget_WaitWhileNVMControllerBusy();
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/* Read the three bytes generated CRC value */
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/* Read the first generated CRC byte value */
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PDITarget_SendByte(PDI_CMD_LDS | (PDI_DATSIZE_4BYTES << 2));
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NVMTarget_SendNVMRegAddress(NVM_REG_DAT0);
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MemoryCRC = PDITarget_ReceiveByte();
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/* Read the second generated CRC byte value */
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PDITarget_SendByte(PDI_CMD_LDS | (PDI_DATSIZE_4BYTES << 2));
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NVMTarget_SendNVMRegAddress(NVM_REG_DAT1);
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MemoryCRC |= ((uint16_t)PDITarget_ReceiveByte() << 8);
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/* Read the third generated CRC byte value */
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PDITarget_SendByte(PDI_CMD_LDS | (PDI_DATSIZE_4BYTES << 2));
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NVMTarget_SendNVMRegAddress(NVM_REG_DAT2);
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MemoryCRC |= ((uint32_t)PDITarget_ReceiveByte() << 16);
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@ -124,15 +120,31 @@ void NVMTarget_ReadMemory(uint32_t ReadAddress, uint8_t* ReadBuffer, uint16_t Re
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{
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NVMTarget_WaitWhileNVMControllerBusy();
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/* Send the READNVM command to the NVM controller for reading of an aribtrary location */
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PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));
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NVMTarget_SendNVMRegAddress(NVM_REG_CMD);
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PDITarget_SendByte(NVM_CMD_READNVM);
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/* TODO: Optimize via REPEAT and buffer orientated commands */
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for (uint16_t i = 0; i < ReadSize; i++)
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{
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/* Send the address of the first location to read from - this also primes the internal address
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* counters so that we can use the REPEAT command later to save on overhead for multiple bytes */
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PDITarget_SendByte(PDI_CMD_LDS | (PDI_DATSIZE_4BYTES << 2));
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NVMTarget_SendAddress(ReadAddress++);
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NVMTarget_SendAddress(ReadAddress);
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*(ReadBuffer++) = PDITarget_ReceiveByte();
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/* Check to see if we are reading more than a single byte */
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if (ReadSize > 1)
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{
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/* Decrement the ReadSize counter as we have already read once byte of memory */
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ReadSize--;
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/* Send the REPEAT command with the specified number of bytes remaining to read */
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PDITarget_SendByte(PDI_CMD_REPEAT | PDI_DATSIZE_2BYTES);
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PDITarget_SendByte(ReadSize & 0xFF);
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PDITarget_SendByte(ReadSize >> 8);
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/* Send a LD command with indirect access and postincrement to read out the remaining bytes */
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PDITarget_SendByte(PDI_CMD_LD | (PDI_POINTER_INDIRECT_PI << 2) | PDI_DATSIZE_1BYTE);
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for (uint16_t i = 1; i < ReadSize; i++)
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*(ReadBuffer++) = PDITarget_ReceiveByte();
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}
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}
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@ -145,6 +157,7 @@ void NVMTarget_EraseMemory(uint8_t EraseCommand, uint32_t Address)
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NVMTarget_SendNVMRegAddress(NVM_REG_CMD);
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PDITarget_SendByte(EraseCommand);
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/* Chip erase is handled seperately, since it's procedure is different to other erase types */
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if (EraseCommand == NVM_CMD_CHIPERASE)
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{
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/* Set CMDEX bit in NVM CTRLA register to start the chip erase */
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@ -160,7 +173,8 @@ void NVMTarget_EraseMemory(uint8_t EraseCommand, uint32_t Address)
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PDITarget_SendByte(0x00);
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}
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NVMTarget_WaitWhileNVMBusBusy();
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/* Wait until both the NVM bus and NVM controller are ready again */
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PDITarget_WaitWhileNVMBusBusy();
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NVMTarget_WaitWhileNVMControllerBusy();
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}
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@ -56,12 +56,7 @@
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#endif
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/* Defines: */
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#define FLASH_BASE 0x00800000
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#define EPPROM_BASE 0x008C0000
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#define FUSE_BASE 0x008F0020
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#define DATAMEM_BASE 0x01000000
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#define PROD_SIGNATURE_BASE 0x008E0200
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#define USER_SIGNATURE_BASE 0x008E0400
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#define NVM_BUSY_TIMEOUT_MS 200
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#define NVM_REG_ADDR0 0x00
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#define NVM_REG_ADDR1 0x01
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@ -113,8 +108,7 @@
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/* Function Prototypes: */
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void NVMTarget_SendNVMRegAddress(uint8_t Register);
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void NVMTarget_SendAddress(uint32_t AbsoluteAddress);
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bool NVMTarget_WaitWhileNVMBusBusy(void);
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void NVMTarget_WaitWhileNVMControllerBusy(void);
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bool NVMTarget_WaitWhileNVMControllerBusy(void);
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uint32_t NVMTarget_GetMemoryCRC(uint8_t MemoryCommand);
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void NVMTarget_ReadMemory(uint32_t ReadAddress, uint8_t* ReadBuffer, uint16_t ReadSize);
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void NVMTarget_EraseMemory(uint8_t EraseCommand, uint32_t Address);
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@ -114,7 +114,7 @@ static void PDIProtocol_EnterXPROGMode(void)
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PDITarget_SendByte(PDI_NVMENABLE_KEY[i - 1]);
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/* Wait until the NVM bus becomes active */
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bool NVMBusEnabled = NVMTarget_WaitWhileNVMBusBusy();
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bool NVMBusEnabled = PDITarget_WaitWhileNVMBusBusy();
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Endpoint_Write_Byte(CMD_XPROG);
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Endpoint_Write_Byte(XPRG_CMD_ENTER_PROGMODE);
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@ -44,7 +44,7 @@ volatile bool IsSending;
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volatile uint16_t SoftUSART_Data;
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volatile uint8_t SoftUSART_BitCount;
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ISR(TIMER0_COMPA_vect, ISR_BLOCK)
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ISR(TIMER1_COMPA_vect, ISR_BLOCK)
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{
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/* Toggle CLOCK pin in a single cycle (see AVR datasheet) */
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BITBANG_PDICLOCK_PIN |= BITBANG_PDICLOCK_MASK;
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@ -112,11 +112,10 @@ void PDITarget_EnableTargetPDI(void)
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asm volatile ("NOP"::);
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asm volatile ("NOP"::);
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/* Fire timer compare ISR every 50 cycles to manage the software USART */
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OCR0A = 50;
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TCCR0A = (1 << WGM01);
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TCCR0B = (1 << CS00);
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TIMSK0 = (1 << OCIE0A);
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/* Fire timer compare ISR every 100 cycles to manage the software USART */
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OCR1A = 100;
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TCCR1B = (1 << WGM12) | (1 << CS10);
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TIMSK1 = (1 << OCIE1A);
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PDITarget_SendBreak();
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PDITarget_SendBreak();
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@ -275,4 +274,20 @@ void PDITarget_SendBreak(void)
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#endif
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}
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bool PDITarget_WaitWhileNVMBusBusy(void)
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{
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TCNT0 = 0;
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/* Poll the STATUS register to check to see if NVM access has been enabled */
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while (TCNT0 < PDI_NVM_TIMEOUT_MS)
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{
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/* Send the LDCS command to read the PDI STATUS register to see the NVM bus is active */
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PDITarget_SendByte(PDI_CMD_LDCS | PDI_STATUS_REG);
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if (PDITarget_ReceiveByte() & PDI_STATUS_NVM)
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return true;
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}
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return false;
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}
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#endif
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@ -69,6 +69,8 @@
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#define BITS_IN_FRAME 12
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#define PDI_NVM_TIMEOUT_MS 200
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#define PDI_CMD_LDS 0x00
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#define PDI_CMD_LD 0x20
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#define PDI_CMD_STS 0x40
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@ -102,5 +104,6 @@
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void PDITarget_SendByte(uint8_t Byte);
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uint8_t PDITarget_ReceiveByte(void);
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void PDITarget_SendBreak(void);
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bool PDITarget_WaitWhileNVMBusBusy(void);
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#endif
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